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Tue, 16 Jul 2024 14:34:22 -0500 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Tue, 16 Jul 2024 14:34:21 -0500 From: Stewart Hildebrand To: Bjorn Helgaas CC: Stewart Hildebrand , , Subject: [PATCH v2 4/8] PCI: Restore memory decoding after reallocation Date: Tue, 16 Jul 2024 15:32:34 -0400 Message-ID: <20240716193246.1909697-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240716193246.1909697-1-stewart.hildebrand@amd.com> References: <20240716193246.1909697-1-stewart.hildebrand@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD2:EE_|SA3PR12MB8045:EE_ X-MS-Office365-Filtering-Correlation-Id: 430d85f6-2e81-4a03-28cf-08dca5ce4c71 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2024 19:34:24.2848 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 430d85f6-2e81-4a03-28cf-08dca5ce4c71 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8045 Currently, the PCI subsystem unconditionally clears the memory decoding bit of devices with resource alignment specified. While drivers should call pci_enable_device() to enable memory decoding, some platforms have devices that expect memory decoding to be enabled even when no driver is bound to the device. It is assumed firmware enables memory decoding in these cases. For example, the vgacon driver uses the 0xb8000 buffer to display a console without any PCI involvement, yet, on some platforms, memory decoding must be enabled on the PCI VGA device in order for the console to be displayed properly. Restore the memory decoding bit after the resource has been reallocated. Signed-off-by: Stewart Hildebrand --- v1->v2: * capitalize subject text * reword commit message Testing notes / how to check if your platform needs memory decoding enabled in order to use vgacon: 1. Boot your system with a monitor attached, without any driver bound to your PCI VGA device. You should see a console on your display. 2. Find the SBDF of your VGA device with lspci -v (00:01.0 in this example). 3. Disable memory decoding (replace 00:01.0 with your SBDF): $ sudo setpci -v -s 00:01.0 0x04.W=0x05 4. Type something to see if it appears on the console display 5. Re-enable memory decoding: $ sudo setpci -v -s 00:01.0 0x04.W=0x07 Relevant prior discussion at [1] [1] https://lore.kernel.org/linux-pci/20160906165652.GE1214@localhost/ --- drivers/pci/pci.c | 1 + drivers/pci/setup-bus.c | 25 +++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 3 files changed, 28 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 53345dc596b5..1ac1435ad91e 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6677,6 +6677,7 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev) pci_read_config_word(dev, PCI_COMMAND, &command); if (command & PCI_COMMAND_MEMORY) { + dev->dev_flags |= PCI_DEV_FLAGS_MEMORY_ENABLE; command &= ~PCI_COMMAND_MEMORY; pci_write_config_word(dev, PCI_COMMAND, command); } diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index ab7510ce6917..6847b251e19a 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -2131,6 +2131,29 @@ pci_root_bus_distribute_available_resources(struct pci_bus *bus, } } +static void restore_memory_decoding(struct pci_bus *bus) +{ + struct pci_dev *dev; + + list_for_each_entry(dev, &bus->devices, bus_list) { + struct pci_bus *b; + + if (dev->dev_flags & PCI_DEV_FLAGS_MEMORY_ENABLE) { + u16 command; + + pci_read_config_word(dev, PCI_COMMAND, &command); + command |= PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, command); + } + + b = dev->subordinate; + if (!b) + continue; + + restore_memory_decoding(b); + } +} + /* * First try will not touch PCI bridge res. * Second and later try will clear small leaf bridge res. @@ -2229,6 +2252,8 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) goto again; dump: + restore_memory_decoding(bus); + /* Dump the resource on buses */ pci_bus_dump_resources(bus); } diff --git a/include/linux/pci.h b/include/linux/pci.h index e83ac93a4dcb..cb5df4c6a999 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -245,6 +245,8 @@ enum pci_dev_flags { PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), /* Device does honor MSI masking despite saying otherwise */ PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), + /* Firmware enabled memory decoding, to be restored if BAR is updated */ + PCI_DEV_FLAGS_MEMORY_ENABLE = (__force pci_dev_flags_t) (1 << 13), }; enum pci_irq_reroute_variant {