From patchwork Tue Jul 16 21:31:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13734967 X-Patchwork-Delegate: kw@linux.com Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F8A514600C for ; Tue, 16 Jul 2024 21:32:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721165544; cv=none; b=fOB7tlokvsOWKvk1/ND5iGe+w+DPHZpc9/2UXxytkOjQL7peUevUTvC1Cm/wNJ4H9/94uGwz4sEUJa1Xnfiu6rY519LGS/ftKR0n+PrtViGrdTNhcbNfxw/MsGfvNsD7vagxMRUZdHjQTWp1hRn17XKrfj6hyYb866zZKdneVJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721165544; c=relaxed/simple; bh=C2p2QHrHO86v8QlhU3nQeNCgnFdoGliH8iSzjZ1qojw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type; b=nKKKnVqsv1w3qQsmkT6g+iVhug9Yk6Z47hnYldyX77DeMIi/WdPUo1W6kCOYWjF5zeCT+1sjqGnQDNFGI93X5hx7yGzS8po1PdhV1qypYeQguK6ugDUTILlA4cBFMQfC4HTkHjuFsLOt/dWm+ynDelDgFBdSTnVSVlJNn3FTkTw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=ImptZRS8; arc=none smtp.client-ip=209.85.210.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="ImptZRS8" Received: by mail-pf1-f173.google.com with SMTP id d2e1a72fcca58-70b0d0a7a56so4590727b3a.0 for ; Tue, 16 Jul 2024 14:32:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1721165542; x=1721770342; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=bDu58s/yu8k7/K65TlDoP49u82ZMCl/2qPk9wT4mQSk=; b=ImptZRS8HPC+ISjz3v9yw+zs0xyJmb87wjcCFWTZjppcYeNYzgxKTFLd+rEyOzpxZ9 e4biQ/bTsWhKJwdHBu+0DDXdfBwy7MScRMIWFxUr3sg2zTK8dr1f7WINppia7jDZadmN cGVsfBLjbcasRQW++zv9835Fp7bslqkCXJpPc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721165542; x=1721770342; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=bDu58s/yu8k7/K65TlDoP49u82ZMCl/2qPk9wT4mQSk=; b=uFa2V6uvgil9mssJbjFaGQ/DJRX9O9RlT/cB+0aRf8vRsORTbCyxathSlcs1VY12AW obYaUwIFqLo2aIcpnZZNS94fAHPCn1lGp2s8qF1RYN7MjglxdEVsGBb7S+NXFmw5EDuZ FtcghxixxW+X8tEETigkPnErXkO4DRIHCM446evZgUbV4DHJ8wHzWFPMU94yA3t4uYdF kIOrry43O+mFmggF0C6w41wQNe04IlyirVMbbkIH7DcM/XBktks7Zu/LE1EF6R2bdO8z XrPP4X9JoiQtlJndNFxhlYG8bSWryTgTPOo5dJriQYgPov6ZCB+KePwKWbPHMFdgvxqT Q1Xg== X-Gm-Message-State: AOJu0YyD1JY34NsnsOlBQqBxj5S9J9IOw/iDs3EQ+EXk++ga6gp1ntRO xzvenLc2xkd3Gyhzw6o4G1F6C+LL6hmYN2z/iZgDl1nnWbs3xsbiAVus/MxrIYYdFcdnVy0O85c pg3c+tCoQr8mxRWqB+ai7uOmojHLEzDZFrnCVTc30oGMqyvAM/JH+pfbDe6pVTjU4MqQkBsEdKa 7PORPvGhAqeK/OQBRJillTFuNESL8F9Q06Pp629bW06BQcvw== X-Google-Smtp-Source: AGHT+IH0Y9+x+k35oeCTVD3LE8/SAcgucMDAoq8oz6zUhM4uRLOH0VIwFmwWNPm22oM56uujdUQQpA== X-Received: by 2002:a05:6a00:2e15:b0:70a:fa4c:4b28 with SMTP id d2e1a72fcca58-70c1fbe1812mr4531776b3a.15.1721165542191; Tue, 16 Jul 2024 14:32:22 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b7eb9e20fsm6812828b3a.31.2024.07.16.14.32.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 14:32:21 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 12/12] PCI: brcmstb: Enable 7712 SOCs Date: Tue, 16 Jul 2024 17:31:27 -0400 Message-Id: <20240716213131.6036-13-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240716213131.6036-1-james.quinlan@broadcom.com> References: <20240716213131.6036-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712). Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Tested-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index fa5616a56383..7debb3599789 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1193,6 +1193,10 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ + /* 7712 does not have this (RGR1) timer */ + if (pcie->model == BCM7712) + return; + /* Each unit in timeout register is 1/216,000,000 seconds */ writel(216 * timeout_us, pcie->base + REG_OFFSET); } @@ -1664,6 +1668,13 @@ static const int pcie_offsets_bmips_7425[] = { [PCIE_INTR2_CPU_BASE] = 0x4300, }; +static const int pcie_offset_bcm7712[] = { + [EXT_CFG_INDEX] = 0x9000, + [EXT_CFG_DATA] = 0x9004, + [PCIE_HARD_DEBUG] = 0x4304, + [PCIE_INTR2_CPU_BASE] = 0x4400, +}; + static const struct pcie_cfg_data generic_cfg = { .offsets = pcie_offsets, .model = GENERIC, @@ -1729,6 +1740,14 @@ static const struct pcie_cfg_data bcm7216_cfg = { .num_inbound = 3, }; +static const struct pcie_cfg_data bcm7712_cfg = { + .offsets = pcie_offset_bcm7712, + .perst_set = brcm_pcie_perst_set_7278, + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, + .model = BCM7712, + .num_inbound = 10, +}; + static const struct of_device_id brcm_pcie_match[] = { { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg }, { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg }, @@ -1738,6 +1757,7 @@ static const struct of_device_id brcm_pcie_match[] = { { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg }, { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg }, + { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg }, {}, };