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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 20:56:10.1030 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 055d737e-b403-415d-83c6-08dca6a2e2fa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9135 When "No ST mode" is enabled, endpoint devices can generate TPH headers but with all steering tags treated as zero. A steering tag of zero is interpreted as "using the default policy" by the root complex. This is essential to quantify the benefit of steering tags for some given workloads. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek --- .../admin-guide/kernel-parameters.txt | 1 + drivers/pci/pci-driver.c | 7 +++++- drivers/pci/pci.c | 12 ++++++++++ drivers/pci/pcie/tph.c | 22 +++++++++++++++++++ include/linux/pci-tph.h | 2 ++ include/linux/pci.h | 1 + 6 files changed, 44 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 65581ebd9b50..1b761f062969 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4656,6 +4656,7 @@ norid [S390] ignore the RID field and force use of one PCI domain per PCI function notph [PCIE] Do not use PCIe TPH + nostmode [PCIE] Force TPH to use No ST Mode pcie_aspm= [PCIE] Forcibly enable or ignore PCIe Active State Power Management. diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 9722d070c0ca..abe66541536e 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -324,8 +324,13 @@ static long local_pci_probe(void *_ddi) pci_dev->driver = pci_drv; rc = pci_drv->probe(pci_dev, ddi->id); if (!rc) { - if (pci_tph_disabled()) + if (pci_tph_disabled()) { pcie_tph_disable(pci_dev); + return rc; + } + + if (pci_tph_nostmode()) + pcie_tph_set_nostmode(pci_dev); return rc; } diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4cbfd5b53be8..8745ce1c4a9a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -160,6 +160,9 @@ static bool pcie_ats_disabled; /* If set, the PCIe TPH capability will not be used. */ static bool pcie_tph_disabled; +/* If TPH is enabled, "No ST Mode" will be enforced. */ +static bool pcie_tph_nostmode; + /* If set, the PCI config space of each device is printed during boot. */ bool pci_early_dump; @@ -175,6 +178,12 @@ bool pci_tph_disabled(void) } EXPORT_SYMBOL_GPL(pci_tph_disabled); +bool pci_tph_nostmode(void) +{ + return pcie_tph_nostmode; +} +EXPORT_SYMBOL_GPL(pci_tph_nostmode); + /* Disable bridge_d3 for all PCIe ports */ static bool pci_bridge_d3_disable; /* Force bridge_d3 for all PCIe ports */ @@ -6881,6 +6890,9 @@ static int __init pci_setup(char *str) } else if (!strcmp(str, "notph")) { pr_info("PCIe: TPH is disabled\n"); pcie_tph_disabled = true; + } else if (!strcmp(str, "nostmode")) { + pr_info("PCIe: TPH No ST Mode is enabled\n"); + pcie_tph_nostmode = true; } else if (!strncmp(str, "cbiosize=", 9)) { pci_cardbus_io_size = memparse(str + 9, &str); } else if (!strncmp(str, "cbmemsize=", 10)) { diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c index ad58a892792c..fb8e2f920712 100644 --- a/drivers/pci/pcie/tph.c +++ b/drivers/pci/pcie/tph.c @@ -13,6 +13,19 @@ #include "../pci.h" +/* Update the ST Mode Select field of TPH Control Register */ +static void set_ctrl_reg_mode_sel(struct pci_dev *pdev, u8 st_mode) +{ + u32 reg_val; + + pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, ®_val); + + reg_val &= ~PCI_TPH_CTRL_MODE_SEL_MASK; + reg_val |= FIELD_PREP(PCI_TPH_CTRL_MODE_SEL_MASK, st_mode); + + pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg_val); +} + /* Update the TPH Requester Enable field of TPH Control Register */ static void set_ctrl_reg_req_en(struct pci_dev *pdev, u8 req_type) { @@ -26,6 +39,15 @@ static void set_ctrl_reg_req_en(struct pci_dev *pdev, u8 req_type) pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg_val); } +void pcie_tph_set_nostmode(struct pci_dev *pdev) +{ + if (!pdev->tph_cap) + return; + + set_ctrl_reg_mode_sel(pdev, PCI_TPH_NO_ST_MODE); + set_ctrl_reg_req_en(pdev, PCI_TPH_REQ_TPH_ONLY); +} + void pcie_tph_disable(struct pci_dev *pdev) { if (!pdev->tph_cap) diff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h index e0b782bda929..8fce3969277c 100644 --- a/include/linux/pci-tph.h +++ b/include/linux/pci-tph.h @@ -11,8 +11,10 @@ #ifdef CONFIG_PCIE_TPH void pcie_tph_disable(struct pci_dev *dev); +void pcie_tph_set_nostmode(struct pci_dev *dev); #else static inline void pcie_tph_disable(struct pci_dev *dev) {} +static inline void pcie_tph_set_nostmode(struct pci_dev *dev) {} #endif #endif /* LINUX_PCI_TPH_H */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 05fbbd9ad6b4..ac58f3919993 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1841,6 +1841,7 @@ static inline bool pci_aer_available(void) { return false; } bool pci_ats_disabled(void); bool pci_tph_disabled(void); +bool pci_tph_nostmode(void); #ifdef CONFIG_PCIE_PTM int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);