Message ID | 20240731143946.3478057-4-matthew.gerlach@linux.intel.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Krzysztof WilczyĆski |
Headers | show |
Series | Add PCIe Root Port support for Agilex family of chips | expand |
On Wed, 31 Jul 2024 09:39:42 -0500, matthew.gerlach@linux.intel.com wrote: > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > Add the compatible bindings for the three variants of Agilex > PCIe Hard IP. > > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > --- > .../devicetree/bindings/pci/altr,pcie-root-port.yaml | 9 +++++++++ > 1 file changed, 9 insertions(+) > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml index 52533fccc134..ca9691ec87d2 100644 --- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml @@ -12,9 +12,18 @@ maintainers: properties: compatible: + description: altr,pcie-root-port-1.0 is used for the Cyclone5 + family of chips. The Stratix10 family of chips is supported + by altr,pcie-root-port-2.0. The Agilex family of chips has + three variants of PCIe Hard IP referred to as the f-tile, p-tile, + and r-tile. + enum: - altr,pcie-root-port-1.0 - altr,pcie-root-port-2.0 + - altr,pcie-root-port-3.0-f-tile + - altr,pcie-root-port-3.0-p-tile + - altr,pcie-root-port-3.0-r-tile reg: items: