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Wed, 7 Aug 2024 10:17:59 -0500 From: Stewart Hildebrand To: Bjorn Helgaas , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Yongji Xie , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: Stewart Hildebrand , , , Subject: [PATCH v3 5/8] x86/PCI: Preserve IORESOURCE_STARTALIGN alignment Date: Wed, 7 Aug 2024 11:17:14 -0400 Message-ID: <20240807151723.613742-6-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240807151723.613742-1-stewart.hildebrand@amd.com> References: <20240807151723.613742-1-stewart.hildebrand@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E66:EE_|MW4PR12MB6756:EE_ X-MS-Office365-Filtering-Correlation-Id: 319bde24-8e79-4cc2-8d0f-08dcb6f420e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026|7416014; X-Microsoft-Antispam-Message-Info: 07LKOlNka9VkwSer+P7P7XRoP3I6uHq5zon40mUYRulUB8UYzN8l/OJP0bBnqms/p9RfS6M9keyKZZuO4AkhZAnNjbNMfQx0gAEYfTvoajQt6Rwk8Xli7bugqj08qINfAbdYZBm5aAoOBw2epSepMOgR21+Ukco+el8jf+utEAO8U40eDBAGD63GhkspDETgRWQ8PNCUAXJ7xgZb47GOtigAdpCQVACpwDJBHM27gYk2UME7u3Vl50nX7AL9UbC/MphEg1+3wrgg19uzS2jBzQkcJvYNvT5ETYm0nzCbGKtxk7/b1EdPxrMnQ9gkdeVjx6xJY8oX2O7HxatapfMPQ1h6oA8HiR9b6lnWG0wJl91eI461Hwh+MvIE3Y6eMC0GtL0uFs9af2k9bdouCL6SvF2nCXCzXWtTJvwJJ/AQPpRjCCglm/zIjMugsD5hajyzedd5WYcdyDQTlssOEZ5aLelHoeD/VrIIKywZ0Az0Qwh4od4zEZI9RutSLZbSZIzJQZtVLfJm9K0CdyRlWbuZQX2ZbVRnpXC1+GOjLgea/zL7ywRzvLK7MnhlE2LyW7LsgufbX2nQ/e6KEKDYJGs5PEOM6SiX4Oxd7XtXTo/nl2I4rq8gh9N3lbCf+AxJQSi1pehTZ9OD5BEp2cA7L9Or4BqSCM9qtKxeoXJmbVj2/l7J52Wnk4ijyUdvFTDQQzm0JN6rxd8c3Pih5Qb/wFaI9v4v9lkZRiyIL9/QP+ylwN2L1Kj7yaOwuERyutJMDnoOf0FZNKqG2Zuu8FOzEtXvx912gBoNpuRoHnkOCavEWpMKL/KkUNIJjCok7opZR2FReGBbxnbI266O3TEAChQvQPNmH7RLr92aIOQLHc1PpEkJf4A6JMLPV7ygKVcquFoL49iY9p7w0drJ309egpG1/15iqQhaTBYpMkO6z3polOXDw7KRta2Fdq5MZrStFHUBlt7NIpznhyEGBB2M++V5uWa5AE38djA34nixlvxobz6szGkNHukhHZ8on6xIee7bxQNI198MAupe5lBCaWsJ/4Tg/bbRs2EkYV9CMP32X2zWJW4VW7pErj0eyb55xOOeE5WobewKl35C8aczB4RYkktLGwcxuypvF72+J6Ed3+ACKm3b2fBqkhr3OYS3q4qK89GTL1NyyqXEmg12rIcdL7qMsgM07yi7Itp9GPVo19iNYMkSRb6ho01cGWiyvwka9o4DL+lA88t5+7y1Fx3dYMyJVQwzRZoczzjnCHKf2U/pJUtXsDyqm1jLiwpkhkfuQx6fG9QLbVTwxzqIMvGjgEiVD8NZltBw1MOZLUC/YynfAHoactTR47XlnRhdHK6+VcvaBJ2RWZE94fCKQuoPK/RvqveJPq9QHQSF23llYHeb9GvbCtAT6ga1vt1nl6Ni+54bqWjzsqJcfmtc78V8BhojZO0VHopHtFF5bVQhJByMdMgRal2hXsymu6eTIrWZ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 15:18:01.9045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 319bde24-8e79-4cc2-8d0f-08dcb6f420e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6756 There is a corner case in pcibios_allocate_dev_resources() where the IORESOURCE_STARTALIGN alignment of memory BAR resources gets overwritten. This does not affect bridge resources. The corner case is not yet possible to trigger on x86, but it will be possible once the default resource alignment changes, and memory BAR resources will start to use IORESOURCE_STARTALIGN. Account for IORESOURCE_STARTALIGN in preparation for changing the default resource alignment. Skip the pcibios_save_fw_addr() call since the resource doesn't contain a valid address when alignment has been requested. The impact of this is that we won't be able to restore the firmware allocated BAR, which does not meet alignment requirements anyway. Signed-off-by: Stewart Hildebrand --- v2->v3: * no change v1->v2: * capitalize subject text * clarify commit message * skip pcibios_save_fw_addr() call --- arch/x86/pci/i386.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c index 3abd55902dbc..13d7f7ac3bde 100644 --- a/arch/x86/pci/i386.c +++ b/arch/x86/pci/i386.c @@ -256,7 +256,7 @@ static void alloc_resource(struct pci_dev *dev, int idx, int pass) if (r->flags & IORESOURCE_PCI_FIXED) { dev_info(&dev->dev, "BAR %d %pR is immovable\n", idx, r); - } else { + } else if (!(r->flags & IORESOURCE_STARTALIGN)) { /* We'll assign a new address later */ pcibios_save_fw_addr(dev, idx, r->start); r->end -= r->start;