| Message ID | 20240809073610.2517-1-linux.amoon@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Manivannan Sadhasivam |
| Headers | show |
| Series | [v2] PCI: dw-rockchip: Enable async probe by default | expand |
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 1170e1107508..7a895b66e4e4 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -616,6 +616,7 @@ static struct platform_driver rockchip_pcie_driver = { .name = "rockchip-dw-pcie", .of_match_table = rockchip_pcie_of_match, .suppress_bind_attrs = true, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, }, .probe = rockchip_pcie_probe, };
Rockchip DWC PCIe driver currently waits for the combo PHY link (PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training during boot, it also waits for the link to be up, which could consume several milliseconds during boot. To optimize boot time, this commit allows asynchronous probing. This change enables the PCIe link establishment to occur in the background while other devices are being probed. Signed-off-by: Anand Moon <linux.amoon@gmail.com> --- v2: update the commit message to describe the changs. --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 + 1 file changed, 1 insertion(+) base-commit: ee9a43b7cfe2d8a3520335fea7d8ce71b8cabd9d