From patchwork Fri Aug 23 12:27:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13775052 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69368185944; Fri, 23 Aug 2024 12:27:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724416079; cv=none; b=CNHp5aCcLc3kHwoQyXBEFC6BK6Txv1BY7UDVhNPKdIjOeXkHZEU90eNIL8oXJ+eDW09QDSmrDI5UeBAoiL3mwIESNyBlcr1BdfqNPbYfEnb6b1Lo3Tsgbih4qSd9I9Ocd3QKdWYbenQkxMOri+ay1/0ePrIffLlA7CeZrtzXsH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724416079; c=relaxed/simple; bh=011XsFEdeCUa0WKVhCJsZ8OiQIe9eikU06sNuCgvDFc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rXQJi3cavo7j1awNFu2GSrp2/xhGYnJYdj8Rzb/v9Rfa3FOCnVuVcXp3XpM8BcpHW3uWaBWtY5zxKdjBljZflTRHsQJ0A/ZHIJGcT3hsD13mcj0ixaKcGc/02UKU6dqs3w7DmL284BjYGWwyd9RLXl8BDjAeLVB7uGxoyL2g2xY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=FfnWZfwA; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="FfnWZfwA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1724416077; x=1755952077; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=011XsFEdeCUa0WKVhCJsZ8OiQIe9eikU06sNuCgvDFc=; b=FfnWZfwAjEUk219tL0hEIh2oaU7T21Eu4E2XwwtyoBxadAZD+WbHbQR/ n3GHYyx3r0WBKs/byCbvfS5JX2HD5iSvHKeHBpNLq/1OxuYV+2GJxKo5m g4b8i7+nn4Qdup/hDX3NZz4UzpgDe2NXS2mqhswSE+n3ZDHjv7OueAWh0 UcR00Wo+u5+9HHHufjYtaxtrrSiKwaJw82n2oa1G+0bkSuXsiVW7+Lqah fqf9dvoNOBjqkuNt0PLwcJd6o/179XKJiikJK1wn0HCV3VPwg+2FDZwW0 sPAjZ6YpUOmK3lVhyFAHcxat5tcDKzidfNJFMngsQGsRDp8Cs7ZLep6nB A==; X-CSE-ConnectionGUID: rDZOZxKYRGu2u+L6hg58hQ== X-CSE-MsgGUID: jXAsNi/aSTuE4B9Kzz5TMQ== X-IronPort-AV: E=Sophos;i="6.10,170,1719903600"; d="scan'208";a="198251694" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Aug 2024 05:27:54 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Aug 2024 05:27:30 -0700 Received: from daire-X570.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Aug 2024 05:27:28 -0700 From: To: , CC: , , , , , , , , , , Subject: [PATCH v9 1/3] PCI: microchip: Fix outbound address translation tables Date: Fri, 23 Aug 2024 13:27:15 +0100 Message-ID: <20240823122717.1159133-2-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240823122717.1159133-1-daire.mcnamara@microchip.com> References: <20240823122717.1159133-1-daire.mcnamara@microchip.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daire McNamara On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of three general-purpose Fabric Interface Controller (FIC) buses that encapsulate an AXI-M interface. That FIC is responsible for managing the translations of the upper 32-bits of the AXI-M address. On MPFS, the Root Port driver needs to take account of that outbound address translation done by the parent FIC bus before setting up its own outbound address translation tables. In all cases on MPFS, the remaining outbound address translation tables are 32-bit only. Limit the outbound address translation tables to 32-bit only. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") Signed-off-by: Daire McNamara Acked-by: Conor Dooley Reviewed-by: Ilpo Jarvinen --- .../pci/controller/plda/pcie-microchip-host.c | 30 ++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 48f60a04b740..fa4c85be21f0 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -21,6 +21,8 @@ #include "../../pci.h" #include "pcie-plda.h" +#define MC_OUTBOUND_TRANS_TBL_MASK GENMASK(31, 0) + /* PCIe Bridge Phy and Controller Phy offsets */ #define MC_PCIE1_BRIDGE_ADDR 0x00008000u #define MC_PCIE1_CTRL_ADDR 0x0000a000u @@ -612,6 +614,27 @@ static void mc_disable_interrupts(struct mc_pcie *port) writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); } +static int mc_pcie_setup_iomems(struct pci_host_bridge *bridge, + struct plda_pcie_rp *port) +{ + void __iomem *bridge_base_addr = port->bridge_addr; + struct resource_entry *entry; + u64 pci_addr; + u32 index = 1; + + resource_list_for_each_entry(entry, &bridge->windows) { + if (resource_type(entry->res) == IORESOURCE_MEM) { + pci_addr = entry->res->start - entry->offset; + plda_pcie_setup_window(bridge_base_addr, index, + entry->res->start & MC_OUTBOUND_TRANS_TBL_MASK, + pci_addr, resource_size(entry->res)); + index++; + } + } + + return 0; +} + static int mc_platform_init(struct pci_config_window *cfg) { struct device *dev = cfg->parent; @@ -622,15 +645,14 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, - resource_size(&cfg->res)); + plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & MC_OUTBOUND_TRANS_TBL_MASK, + 0, resource_size(&cfg->res)); /* Need some fixups in config space */ mc_pcie_enable_msi(port, cfg->win); /* Configure non-config space outbound ranges */ - ret = plda_pcie_setup_iomems(bridge, &port->plda); + ret = mc_pcie_setup_iomems(bridge, &port->plda); if (ret) return ret;