| Message ID | 20240826-2160r2-v1-2-106340d538d6@nxp.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | arm64: dts: PCI: lx2160 use fsl,lx2160ar2-pcie | expand |
On Mon, Aug 26, 2024 at 05:38:33PM -0400, Frank Li wrote: > Add rev2 dtsi. Although uboot fixup can change compatible string > fsl,lx2160a-pcie to fsl,ls2088a-pcie since 2019, it is quite confused and > should correctly reflect hardware status. So add fsl-lx2160a-rev2.dtsi to > overwrite pcie's compatible string. > > Add PCIe EP nodes. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- Shawn: Do you have chance to check this? best regards Frank > .../arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 170 +++++++++++++++++++++ > arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 +- > 2 files changed, 171 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi > new file mode 100644 > index 0000000000000..432e54f6f7ae5 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi > @@ -0,0 +1,170 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +// > +// Device Tree file for LX2160 REV2 > +// > +// Copyright 2025 NXP > + > +/dts-v1/; > + > +#include "fsl-lx2160a.dtsi" > + > +&pcie1 { > + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ > + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ > + reg-names = "regs", "config"; > + > + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 > + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; > + > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "intr"; > + > + /delete-property/ apio-wins; > + /delete-property/ ppio-wins; > +}; > + > +&pcie2 { > + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; > + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ > + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ > + reg-names = "regs", "config"; > + > + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 > + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; > + > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "intr"; > + > + /delete-property/ apio-wins; > + /delete-property/ ppio-wins; > +}; > + > +&pcie3 { > + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; > + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ > + 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ > + reg-names = "regs", "config"; > + > + ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000 > + 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; > + > + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "intr"; > + > + /delete-property/ apio-wins; > + /delete-property/ ppio-wins; > +}; > + > + > +&pcie4 { > + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; > + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ > + 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ > + reg-names = "regs", "config"; > + > + ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000 > + 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; > + > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "intr"; > + > + /delete-property/ apio-wins; > + /delete-property/ ppio-wins; > +}; > + > +&pcie5 { > + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; > + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ > + 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ > + reg-names = "regs", "config"; > + > + ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000 > + 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; > + > + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "intr"; > + > + /delete-property/ apio-wins; > + /delete-property/ ppio-wins; > +}; > + > +&pcie6 { > + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; > + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ > + 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ > + reg-names = "regs", "config"; > + > + ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000 > + 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; > + > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "intr"; > + > + /delete-property/ apio-wins; > + /delete-property/ ppio-wins; > +}; > + > +&soc { > + pcie_ep1: pcie-ep@3400000 { > + compatible = "fsl,lx2160ar2-pcie-ep"; > + reg = <0x00 0x03400000 0x0 0x00100000 > + 0x80 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ob-windows = <8>; > + num-ib-windows = <8>; > + status = "disabled"; > + }; > + > + pcie_ep2: pcie-ep@3500000 { > + compatible = "fsl,lx2160ar2-pcie-ep"; > + reg = <0x00 0x03500000 0x0 0x00100000 > + 0x88 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ob-windows = <8>; > + num-ib-windows = <8>; > + status = "disabled"; > + }; > + > + pcie_ep3: pcie-ep@3600000 { > + compatible = "fsl,lx2160ar2-pcie-ep"; > + reg = <0x00 0x03600000 0x0 0x00100000 > + 0x90 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ob-windows = <256>; > + num-ib-windows = <24>; > + status = "disabled"; > + }; > + > + pcie_ep4: pcie-ep@3700000 { > + compatible = "fsl,lx2160ar2-pcie-ep"; > + reg = <0x00 0x03700000 0x0 0x00100000 > + 0x98 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ob-windows = <8>; > + num-ib-windows = <8>; > + status = "disabled"; > + }; > + > + > + pcie_ep5: pcie-ep@3800000 { > + compatible = "fsl,lx2160ar2-pcie-ep"; > + reg = <0x00 0x03800000 0x0 0x00100000 > + 0xa0 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ob-windows = <256>; > + num-ib-windows = <24>; > + status = "disabled"; > + }; > + > + pcie_ep6: pcie-ep@3900000 { > + compatible = "fsl,lx2160ar2-pcie-ep"; > + reg = <0x00 0x03900000 0x0 0x00100000 > + 0xa8 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ob-windows = <8>; > + num-ib-windows = <8>; > + status = "disabled"; > + }; > +}; > + > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > index 26c7ca31e22e7..b2dea03e1b8ec 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > @@ -613,7 +613,7 @@ cluster2-3-crit { > }; > }; > > - soc { > + soc: soc { > compatible = "simple-bus"; > #address-cells = <2>; > #size-cells = <2>; > > -- > 2.34.1 >
On Mon, Aug 26, 2024 at 05:38:33PM -0400, Frank Li wrote: > Add rev2 dtsi. Although uboot fixup can change compatible string > fsl,lx2160a-pcie to fsl,ls2088a-pcie since 2019, it is quite confused and > should correctly reflect hardware status. So add fsl-lx2160a-rev2.dtsi to > overwrite pcie's compatible string. > > Add PCIe EP nodes. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> Applied, thanks!
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi new file mode 100644 index 0000000000000..432e54f6f7ae5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2160 REV2 +// +// Copyright 2025 NXP + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +&pcie1 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; + + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie2 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; + + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie3 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; + + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + + +&pcie4 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; + + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie5 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; + + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie6 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; + + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&soc { + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; + + pcie_ep2: pcie-ep@3500000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000 + 0x88 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; + + pcie_ep3: pcie-ep@3600000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x00100000 + 0x90 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + num-ib-windows = <24>; + status = "disabled"; + }; + + pcie_ep4: pcie-ep@3700000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03700000 0x0 0x00100000 + 0x98 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; + + + pcie_ep5: pcie-ep@3800000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03800000 0x0 0x00100000 + 0xa0 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + num-ib-windows = <24>; + status = "disabled"; + }; + + pcie_ep6: pcie-ep@3900000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03900000 0x0 0x00100000 + 0xa8 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 26c7ca31e22e7..b2dea03e1b8ec 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -613,7 +613,7 @@ cluster2-3-crit { }; }; - soc { + soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>;
Add rev2 dtsi. Although uboot fixup can change compatible string fsl,lx2160a-pcie to fsl,ls2088a-pcie since 2019, it is quite confused and should correctly reflect hardware status. So add fsl-lx2160a-rev2.dtsi to overwrite pcie's compatible string. Add PCIe EP nodes. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- .../arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 170 +++++++++++++++++++++ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 +- 2 files changed, 171 insertions(+), 1 deletion(-)