From patchwork Fri Aug 30 08:11:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 13784516 X-Patchwork-Delegate: manivannanece23@gmail.com Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B951B17332B; Fri, 30 Aug 2024 08:12:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725005566; cv=none; b=dCxlc40s6xBqRQAblWwxIsYfIb0R0JUDxPtINVNY+O7ZG1vkXwuZ7DfIm+ccdrnyTyDuJYOx2mWzf7QOozvzcqwemSSTR8zO2Hyo42UaAkLGTRvWUHeGul9sDhOM4cWOQtlPIu4irA0wLU7eqPB/wY5G2nXxfZyVHRxganJM1T0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725005566; c=relaxed/simple; bh=zBNqpsHdFyk6yvmJb9R1VW5S+KZbjfhFDzG4xyI+rVI=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DvgPX1OYjk8jDiuw5qoLI8sE05+JKu1xd2VH8FhOM38oniXb6+SGae2dC0kAwofM6EsrFuk4eZaBLJNLSpsSOeHnMUSAhRsDIHSVMS7WH90v8kg5hcKi3KfiRCukLQ8fF2nUEgUSotrv2TOpPrFDW0JJTbnL8zT56XgKfOZAsMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=SNh3u2JX; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="SNh3u2JX" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47U7dlgI005704; Fri, 30 Aug 2024 08:12:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= lr+QWxMdKeP6qioVqO6OVYkyHTX85+b5VTFTxwM7AMk=; b=SNh3u2JXebTOnAiF X0BKqpb8TyPb+rXn3eRXBJKFOLb3zdBnGSxsbmSUeQSX5R3dfZ4eacnavsJ7PPXg lXRYcp8TYAS8zD8nVzXK2xItdAoTGUOxQTcuFxtujWdMlNlUmnq8Hzk0wFgQrc+s TdHs3lflfkfGseYcY2J6gzLOuA8bHQ5EJpRl3ezI/ulYe67uBPGVql9MyOW3xKfL ZwcW90DzgddpnpiWcMfK73tmqWWv9dY7byH5g/tek8Eg6oezEZ1Id38WeEGusNsy 8jLc9RCvEQPyjO8SC9aPzgjkWt5kbOhL07WaqjhYHD41/h5XJnpi7X3toX8IDdqp 2HJbTg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419putyywp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 Aug 2024 08:12:30 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47U8CTvs009533 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 Aug 2024 08:12:29 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 Aug 2024 01:12:23 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH V3 6/6] arm64: dts: qcom: ipq5018: Enable PCIe Date: Fri, 30 Aug 2024 13:41:32 +0530 Message-ID: <20240830081132.4016860-7-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240830081132.4016860-1-quic_srichara@quicinc.com> References: <20240830081132.4016860-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DkK4y_SFAmYLv_SlzsVoVAY6V1aNdZVN X-Proofpoint-GUID: DkK4y_SFAmYLv_SlzsVoVAY6V1aNdZVN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-30_04,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=992 suspectscore=0 phishscore=0 spamscore=0 bulkscore=0 clxscore=1015 mlxscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408300060 From: Nitheesh Sekar Enable the PCIe controller and PHY nodes for RDP 432-c2. Signed-off-by: Nitheesh Sekar Signed-off-by: Sricharan Ramabadhran --- [V3] Added perst/wake pins .../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index 8460b538eb6a..602c3c2d6ca3 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -28,6 +28,19 @@ &blsp1_uart1 { status = "okay"; }; +&pcie1 { + pinctrl-0 = <&pcie1_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_x2phy { + status = "okay"; +}; + &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; @@ -43,6 +56,30 @@ &sleep_clk { }; &tlmm { + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio17"; + function = "pcie1_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio15"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + + wake-n-pins { + pins = "gpio19"; + function = "pcie1_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio9";