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Thu, 19 Sep 2024 22:03:53 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%4]) with mapi id 15.20.7982.018; Thu, 19 Sep 2024 22:03:53 +0000 From: Frank Li Date: Thu, 19 Sep 2024 18:03:03 -0400 Subject: [PATCH 3/9] of: address: Add device type pci-ep Message-Id: <20240919-pcie_ep_range-v1-3-b3e9d62780b7@nxp.com> References: <20240919-pcie_ep_range-v1-0-b3e9d62780b7@nxp.com> In-Reply-To: <20240919-pcie_ep_range-v1-0-b3e9d62780b7@nxp.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Abraham I , Saravana Kannan , Jingoo Han , Gustavo Pimentel , Jesper Nilsson , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, =?utf-8?q?Krzys?= =?utf-8?q?ztof_Wilczy=C5=84ski?= , Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; 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Many PCI controllers are dual-role controllers, supporting both Root Complex (RC) and Endpoint (EP) modes. The EP side also needs similar information for proper address translation. Add device type 'pci-ep' and use the same PCI address parser function to parser PCI EP's ranges property. Signed-off-by: Frank Li --- drivers/of/address.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/of/address.c b/drivers/of/address.c index d886f16df8a6e..c98e212d53dc1 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -117,13 +117,13 @@ static int of_bus_default_flags_translate(__be32 *addr, u64 offset, int na) return of_bus_default_translate(addr + 1, offset, na - 1); } -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) || defined(CONFIG_PCI_ENDPOINT) static unsigned int of_bus_pci_get_flags(const __be32 *addr) { unsigned int flags = 0; u32 w = be32_to_cpup(addr); - if (!IS_ENABLED(CONFIG_PCI)) + if (!IS_ENABLED(CONFIG_PCI) && !IS_ENABLED(CONFIG_PCI_ENDPOINT)) return 0; switch((w >> 24) & 0x03) { @@ -172,6 +172,11 @@ static int of_bus_pci_match(struct device_node *np) of_node_is_pcie(np, "pcie"); } +static int of_bus_pci_ep_match(struct device_node *np) +{ + return of_node_is_type(np, "pci-ep") || of_node_is_pcie(np, "pcie-ep"); +} + static void of_bus_pci_count_cells(struct device_node *np, int *addrc, int *sizec) { @@ -196,7 +201,7 @@ static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns, return of_bus_default_map(addr, range, na, ns, pna, fna); } -#endif /* CONFIG_PCI */ +#endif /* CONFIG_PCI || CONFIG_PCI_ENDPOINT */ static int __of_address_resource_bounds(struct resource *r, u64 start, u64 size) { @@ -354,6 +359,19 @@ static struct of_bus of_busses[] = { .get_flags = of_bus_pci_get_flags, }, #endif /* CONFIG_PCI */ +#ifdef CONFIG_PCI_ENDPOINT + /* PCI Endpoint */ + { + .name = "pci-ep", + .addresses = "assigned-addresses", + .match = of_bus_pci_ep_match, + .count_cells = of_bus_pci_count_cells, + .map = of_bus_pci_map, + .translate = of_bus_default_flags_translate, + .flag_cells = 1, + .get_flags = of_bus_pci_get_flags, + }, +#endif /* CONFIG_PCI_EP */ /* ISA */ { .name = "isa",