From patchwork Thu Oct 3 13:25:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Agarwal X-Patchwork-Id: 13821029 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4650F770F1 for ; Thu, 3 Oct 2024 13:25:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727961910; cv=none; b=nvR8C/u84p8rYGG0yZoUyot7EqjNJxVUEX7nLFGtI4IDKPqP/4G325CN+NTrK1TteMs84fYu3do2Z1d6pPgrqyrdSQ5zwUoY4LsRuQDxjAXV4nj35ieRvGT1EXKLKzzRAzOLT+t3c2hp1B9xvQQl1usn/fODQGT7pdE1m1NKTXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727961910; c=relaxed/simple; bh=VPUjdiRcKhVbXwzbnaYMfTxReg621DW/jEbJgfTtIQE=; h=Date:Mime-Version:Message-ID:Subject:From:To:Cc:Content-Type; b=mJe2ziTPNLqO8OIPIwhRxdZq+i6AXZo5OZ6RiDkvR+kl6mv0gI0+TaRE62lwWwhj2ZuOOJd2wse+n0PtXzQ2Rvd/KAxA82ok/D6B/jU9voATTvltynfs8kbllRf5X0kyCRNTowmCJSH1M/jN+6PGX5DXEvJiRd1CQ/cUU69rZjo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--ajayagarwal.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=mIiQpTYB; arc=none smtp.client-ip=209.85.219.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--ajayagarwal.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="mIiQpTYB" Received: by mail-yb1-f202.google.com with SMTP id 3f1490d57ef6-e288a73e967so496066276.1 for ; Thu, 03 Oct 2024 06:25:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1727961908; x=1728566708; darn=vger.kernel.org; h=cc:to:from:subject:message-id:mime-version:date:from:to:cc:subject :date:message-id:reply-to; bh=zhPO6EQNqmZYglwSSc/PcDhcDIT9wXF3yWHj9Joov4E=; b=mIiQpTYBER0QM2yov2WRsB35tdfopxz0AS4VzHo6v1GtIpLZLI/RnZ87ArO4fg1mdc 6ZOGvCFaYQ9WEWlDVRaW/z1KsahI70OBs8ocA+BWblt45+JsyYxiReUH3Kb0eWVcI8NW 4cy47kD+tjdfC924Gw8XMznnxauQoUXW3hP+nXfJHeJWnt6/oqxkZBI/MuQB7puL0cJc FScWNnj/mwnS7u+tI0k2J0eQhO/qppOl8RIfiiHvqlUOfEfh6GwWTjao3aqhtAEx/NHm 5IDMEHAPEEtG7fC39j1TdnP/L2PjlVLvaIQZ62hGWDsqzjSD8tAaaEQE5zQKIhMh20ui Uebg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727961908; x=1728566708; h=cc:to:from:subject:message-id:mime-version:date:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=zhPO6EQNqmZYglwSSc/PcDhcDIT9wXF3yWHj9Joov4E=; b=GRSLVl58gozzd2UX3kAJGBz+yDt8RhvBPk6SLjkBT8JoGBdoZjgy58SvmnGxlAaFLm vuJTLKl53b1HqlV8UmwPoKcavxeJZU5Vj8ntUEAx//D8dxm8EOp6ywziV/hD2c7FCJp+ BZ7XXNXwZsCjexu+GCzcuHEprgzpCqD99HZ+IECnXMOcG3RNtEO8TI9qhPdUO6Vt51Uc nzPqd6aOyoO9NSKCVUiFZuD0ESHAudk/q9i8CBC1CbKyv4k5tca8/e/IwfQFfiD1mqIh 0N15CRKp1Dvu9C4e7mYQiNmgXWCFL5WCmbZBgnGZmstkJVs6AQXSfWyHCCC6i52f/6L6 Wzpw== X-Gm-Message-State: AOJu0YzOwYGecWbh58IqBKBHxRvtj2JN61W6KvFoK9+w6lNybNaIeqbm 6+3nU2wzqFF0Q0LwmRPkmLGVG+s+kPx9ZzAYpps0g1da/5XXwtoj7H5ZIVNH4izi6sT+3qXUguQ mCpxofEpmPHDVrLCz9NjyBQ== X-Google-Smtp-Source: AGHT+IGjc/KJTG0s+tgCvOkKPffMgNe2i691hL28KU5K79OZJJtzI9Nr9BgjkwwAjuJfaIhwIcAIYcuUHVlPMn7wKA== X-Received: from ajaya.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:39b5]) (user=ajayagarwal job=sendgmr) by 2002:a25:a283:0:b0:e11:7246:963b with SMTP id 3f1490d57ef6-e26383802femr22279276.1.1727961908261; Thu, 03 Oct 2024 06:25:08 -0700 (PDT) Date: Thu, 3 Oct 2024 18:55:03 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Message-ID: <20241003132503.2279433-1-ajayagarwal@google.com> Subject: [PATCH v2] PCI/ASPM: Disable L1 before disabling L1ss From: Ajay Agarwal To: " =?utf-8?q?Ilpo_J=C3=A4rvinen?= " , "David E. Box" , Johan Hovold , Manivannan Sadhasivam , Bjorn Helgaas , Manu Gautam , Sajid Dalvi , Heiner Kallweit , Vidya Sagar , Shuai Xue Cc: linux-pci@vger.kernel.org, Ajay Agarwal The current sequence in the driver for L1ss update is as follows. Disable L1ss Disable L1 Enable L1ss as required Enable L1 if required With this sequence, a bus hang is observed during the L1ss disable sequence when the RC CPU attempts to clear the RC L1ss register after clearing the EP L1ss register. It looks like the RC attempts to enter L1ss again and at the same time, access to RC L1ss register fails because aux clk is still not active. PCIe spec r6.2, section 5.5.4, recommends that setting either or both of the enable bits for ASPM L1 PM Substates must be done while ASPM L1 is disabled. My interpretation here is that clearing L1ss should also be done when L1 is disabled. Thereby, change the sequence as follows. Disable L1 Disable L1ss Enable L1ss as required Enable L1 if required Signed-off-by: Ajay Agarwal --- drivers/pci/pcie/aspm.c | 50 ++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 26 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index cee2365e54b8..c172886129f3 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -848,17 +848,13 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) /* Configure the ASPM L1 substates */ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) { - u32 val, enable_req; + u32 val; struct pci_dev *child = link->downstream, *parent = link->pdev; - enable_req = (link->aspm_enabled ^ state) & state; - /* - * Here are the rules specified in the PCIe spec for enabling L1SS: + * Spec r6.2, section 5.5.4, mentions the rules for enabling L1SS: * - When enabling L1.x, enable bit at parent first, then at child * - When disabling L1.x, disable bit at child first, then at parent - * - When enabling ASPM L1.x, need to disable L1 - * (at child followed by parent). * - The ASPM/PCIPM L1.2 must be disabled while programming timing * parameters * @@ -871,16 +867,6 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) PCI_L1SS_CTL1_L1SS_MASK, 0); pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, PCI_L1SS_CTL1_L1SS_MASK, 0); - /* - * If needed, disable L1, and it gets enabled later - * in pcie_config_aspm_link(). - */ - if (enable_req & (PCIE_LINK_STATE_L1_1 | PCIE_LINK_STATE_L1_2)) { - pcie_capability_clear_word(child, PCI_EXP_LNKCTL, - PCI_EXP_LNKCTL_ASPM_L1); - pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, - PCI_EXP_LNKCTL_ASPM_L1); - } val = 0; if (state & PCIE_LINK_STATE_L1_1) @@ -937,21 +923,33 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) dwstream |= PCI_EXP_LNKCTL_ASPM_L1; } + /* + * Spec r6.2, section 5.5.4, recommends that setting either or both of + * the enable bits for ASPM L1 PM Substates must be done while ASPM L1 + * is disabled. So disable L1 here, and it gets enabled later after the + * L1ss configuration has been completed. + * + * Spec r6.2, section 7.5.3.7, mentions that ASPM L1 must be enabled by + * software in the Upstream component on a Link prior to enabling ASPM + * L1 in the Downstream component on the Link. When disabling L1, + * software must disable ASPM L1 in the Downstream component on a Link + * prior to disabling ASPM L1 in the Upstream component on that Link. + * + * Spec doesn't mention L0s. + * + * Disable L1 and L0s here, and they get enabled later after the L1ss + * configuration has been completed. + */ + list_for_each_entry(child, &linkbus->devices, bus_list) + pcie_config_aspm_dev(child, 0); + pcie_config_aspm_dev(parent, 0); + if (link->aspm_capable & PCIE_LINK_STATE_L1SS) pcie_config_aspm_l1ss(link, state); - /* - * Spec 2.0 suggests all functions should be configured the - * same setting for ASPM. Enabling ASPM L1 should be done in - * upstream component first and then downstream, and vice - * versa for disabling ASPM L1. Spec doesn't mention L0S. - */ - if (state & PCIE_LINK_STATE_L1) - pcie_config_aspm_dev(parent, upstream); + pcie_config_aspm_dev(parent, upstream); list_for_each_entry(child, &linkbus->devices, bus_list) pcie_config_aspm_dev(child, dwstream); - if (!(state & PCIE_LINK_STATE_L1)) - pcie_config_aspm_dev(parent, upstream); link->aspm_enabled = state;