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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B071.mail.protection.outlook.com (10.167.243.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Tue, 8 Oct 2024 22:19:39 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 8 Oct 2024 17:19:38 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 14/15] cxl/aer/pci: Export pci_aer_unmask_internal_errors() Date: Tue, 8 Oct 2024 17:16:56 -0500 Message-ID: <20241008221657.1130181-15-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B071:EE_|DS7PR12MB5933:EE_ X-MS-Office365-Filtering-Correlation-Id: eb7182a3-222b-4b78-d284-08dce7e74d11 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:19:39.5618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb7182a3-222b-4b78-d284-08dce7e74d11 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5933 The CXL driver needs to enable AER correctable and uncorrectable internal errors in order to receive notification of protocol errors. pci_aer_unmask_internal_errors() is currently defined as 'static' in the AER service driver. Update the AER service driver, exporting pci_aer_unmask_internal_errors() to CXL namespace. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- drivers/pci/pcie/aer.c | 6 ++++-- include/linux/aer.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 81a19028c4e7..1b4004932084 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -962,7 +962,6 @@ static bool is_internal_error(struct aer_err_info *info) return info->status & PCI_ERR_UNC_INTN; } -#ifdef CONFIG_PCIEAER_CXL /** * pci_aer_unmask_internal_errors - unmask internal errors * @dev: pointer to the pcie_dev data structure @@ -973,7 +972,7 @@ static bool is_internal_error(struct aer_err_info *info) * Note: AER must be enabled and supported by the device which must be * checked in advance, e.g. with pcie_aer_is_native(). */ -static void pci_aer_unmask_internal_errors(struct pci_dev *dev) +void pci_aer_unmask_internal_errors(struct pci_dev *dev) { int aer = dev->aer_cap; u32 mask; @@ -986,6 +985,9 @@ static void pci_aer_unmask_internal_errors(struct pci_dev *dev) mask &= ~PCI_ERR_COR_INTERNAL; pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); } +EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, CXL); + +#ifdef CONFIG_PCIEAER_CXL static bool is_cxl_mem_dev(struct pci_dev *dev) { diff --git a/include/linux/aer.h b/include/linux/aer.h index 67fd04c5ae2b..c43d2b60b992 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -69,5 +69,7 @@ struct cxl_port_err_hndlrs { void register_cxl_port_hndlrs(struct cxl_port_err_hndlrs *_cxl_port_hndlrs); void unregister_cxl_port_hndlrs(void); struct cxl_port_err_hndlrs *find_cxl_port_hndlrs(void); + +void pci_aer_unmask_internal_errors(struct pci_dev *dev); #endif //_AER_H_