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Fri, 18 Oct 2024 11:22:52 -0700 (PDT) Received: from stbsrv-and-02.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cde114d782sm9307616d6.46.2024.10.18.11.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 11:22:51 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/1] RFC: dt bindings: Add property "brcm,gen3-eq-presets" Date: Fri, 18 Oct 2024 14:22:45 -0400 Message-ID: <20241018182247.41130-2-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241018182247.41130-1-james.quinlan@broadcom.com> References: <20241018182247.41130-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Support configuration of the GEN3 preset equalization settings, aka the Lane Equalization Control Register(s) of the Secondary PCI Express Extended Capability. These registers are of type HwInit/RsvdP and typically set by FW. In our case they are set by our RC host bridge driver using internal registers. Signed-off-by: Jim Quinlan --- .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 0925c520195a..f965ad57f32f 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -104,6 +104,18 @@ properties: minItems: 1 maxItems: 3 + brcm,gen3-eq-presets: + description: | + A u16 array giving the GEN3 equilization presets, one for each lane. + These values are destined for the 16bit registers known as the + Lane Equalization Control Register(s) of the Secondary PCI Express + Extended Capability. In the array, lane 0 is first term, lane 1 next, + etc. The contents of the entries reflect what is necessary for + the current board and SoC, and the details of each preset are + described in Section 7.27.4 of the PCI base spec, Revision 3.0. + + $ref: /schemas/types.yaml#/definitions/uint16-array + required: - compatible - reg