| Message ID | 20241025210305.27499-8-terry.bowman@amd.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | Enable CXL PCIe port protocol error handling and logging | expand |
On Fri, 25 Oct 2024 16:02:58 -0500 Terry Bowman <terry.bowman@amd.com> wrote: > Existing recovery procedure for PCIe uncorrectable errors (UCE) does not > apply to CXL devices. Recovery can not be used for CXL devices because of > the potential for corruption on what can be system memory. Also, current > PCIe UCE recovery does not begin at the bridge but begins at the bridge's > first downstream device. I'm still stuck on why it is fine for PCIe to skip handling errors in the root port. Can't see why it should be different. I might take a poke at what happens on an emulated PCIe system to try and understand this better but probably not that quickly. Without understanding the reasoning behind that I'm reluctant to make an assessment of whether this code is right. One trivial comment inline. Jonathan > This will miss handling CXL protocol errors in a > CXL root port. A separate CXL recovery is needed because of the different > handling requirements > > Add a new function, cxl_do_recovery() using the following. > > Add cxl_walk_bridge() to iterate the detected error's sub-topology. > cxl_walk_bridge() is similar to pci_walk_bridge() but the CXL flavor > will begin iteration at the bridge rather than beginning at the > bridge's first downstream child. > > Add cxl_report_error_detected() as an analog to report_error_detected(). > It will call pci_driver::cxl_err_handlers for each iterated downstream > child. The pci_driver::cxl_err_handlers UCE handler returns a boolean > indicating if there was a UCE error detected during handling. > > cxl_do_recovery() uses the status from cxl_report_error_detected() to > determine how to proceed. Non-fatal CXL UCE errors will be treated as > fatal. If a UCE was present during handling then cxl_do_recovery() > will kernel panic. > > Signed-off-by: Terry Bowman <terry.bowman@amd.com> > --- > drivers/pci/pci.h | 3 +++ > drivers/pci/pcie/aer.c | 5 +++- > drivers/pci/pcie/err.c | 54 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 61 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index 14d00ce45bfa..5a67e41919d8 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -658,6 +658,9 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, > pci_channel_state_t state, > pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); > > +/* CXL error reporting and handling */ > +void cxl_do_recovery(struct pci_dev *dev); > + > bool pcie_wait_for_link(struct pci_dev *pdev, bool active); > int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); > > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index d772f123c6a2..19432ab2cfb6 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -1048,7 +1048,10 @@ static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) > pdrv->cxl_err_handler->cor_error_detected(dev); > > pcie_clear_device_status(dev); > - } > + } else if (info->severity == AER_NONFATAL) > + cxl_do_recovery(dev); > + else if (info->severity == AER_FATAL) Needs {} > + cxl_do_recovery(dev); > } > > static int handles_cxl_error_iter(struct pci_dev *dev, void *data) > diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c > index 31090770fffc..3785f4ca5103 100644 > --- a/drivers/pci/pcie/err.c > +++ b/drivers/pci/pcie/err.c > @@ -276,3 +276,57 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, > > return status; > } > + > +static void cxl_walk_bridge(struct pci_dev *bridge, > + int (*cb)(struct pci_dev *, void *), > + void *userdata) > +{ > + bool *status = userdata; > + > + cb(bridge, status); > + if (bridge->subordinate && !*status) > + pci_walk_bus(bridge->subordinate, cb, status); > +} > + > +static int cxl_report_error_detected(struct pci_dev *dev, void *data) > +{ > + struct pci_driver *pdrv = dev->driver; > + bool *status = data; > + > + device_lock(&dev->dev); > + if (pdrv && pdrv->cxl_err_handler && > + pdrv->cxl_err_handler->error_detected) { > + const struct cxl_error_handlers *cxl_err_handler = > + pdrv->cxl_err_handler; > + *status |= cxl_err_handler->error_detected(dev); > + } > + device_unlock(&dev->dev); > + return *status; > +} > + > +void cxl_do_recovery(struct pci_dev *dev) > +{ > + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); > + int type = pci_pcie_type(dev); > + struct pci_dev *bridge; > + int status; > + > + if (type == PCI_EXP_TYPE_ROOT_PORT || > + type == PCI_EXP_TYPE_DOWNSTREAM || > + type == PCI_EXP_TYPE_UPSTREAM || > + type == PCI_EXP_TYPE_ENDPOINT) > + bridge = dev; > + else > + bridge = pci_upstream_bridge(dev); > + > + cxl_walk_bridge(bridge, cxl_report_error_detected, &status); > + if (status) > + panic("CXL cachemem error. Invoking panic"); > + > + if (host->native_aer || pcie_ports_native) { > + pcie_clear_device_status(dev); > + pci_aer_clear_nonfatal_status(dev); > + } > + > + pci_info(bridge, "No uncorrectable error found. Continuing.\n"); > +}
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 14d00ce45bfa..5a67e41919d8 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -658,6 +658,9 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, pci_channel_state_t state, pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); +/* CXL error reporting and handling */ +void cxl_do_recovery(struct pci_dev *dev); + bool pcie_wait_for_link(struct pci_dev *pdev, bool active); int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index d772f123c6a2..19432ab2cfb6 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1048,7 +1048,10 @@ static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) pdrv->cxl_err_handler->cor_error_detected(dev); pcie_clear_device_status(dev); - } + } else if (info->severity == AER_NONFATAL) + cxl_do_recovery(dev); + else if (info->severity == AER_FATAL) + cxl_do_recovery(dev); } static int handles_cxl_error_iter(struct pci_dev *dev, void *data) diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index 31090770fffc..3785f4ca5103 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -276,3 +276,57 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, return status; } + +static void cxl_walk_bridge(struct pci_dev *bridge, + int (*cb)(struct pci_dev *, void *), + void *userdata) +{ + bool *status = userdata; + + cb(bridge, status); + if (bridge->subordinate && !*status) + pci_walk_bus(bridge->subordinate, cb, status); +} + +static int cxl_report_error_detected(struct pci_dev *dev, void *data) +{ + struct pci_driver *pdrv = dev->driver; + bool *status = data; + + device_lock(&dev->dev); + if (pdrv && pdrv->cxl_err_handler && + pdrv->cxl_err_handler->error_detected) { + const struct cxl_error_handlers *cxl_err_handler = + pdrv->cxl_err_handler; + *status |= cxl_err_handler->error_detected(dev); + } + device_unlock(&dev->dev); + return *status; +} + +void cxl_do_recovery(struct pci_dev *dev) +{ + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); + int type = pci_pcie_type(dev); + struct pci_dev *bridge; + int status; + + if (type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_DOWNSTREAM || + type == PCI_EXP_TYPE_UPSTREAM || + type == PCI_EXP_TYPE_ENDPOINT) + bridge = dev; + else + bridge = pci_upstream_bridge(dev); + + cxl_walk_bridge(bridge, cxl_report_error_detected, &status); + if (status) + panic("CXL cachemem error. Invoking panic"); + + if (host->native_aer || pcie_ports_native) { + pcie_clear_device_status(dev); + pci_aer_clear_nonfatal_status(dev); + } + + pci_info(bridge, "No uncorrectable error found. Continuing.\n"); +}
Existing recovery procedure for PCIe uncorrectable errors (UCE) does not apply to CXL devices. Recovery can not be used for CXL devices because of the potential for corruption on what can be system memory. Also, current PCIe UCE recovery does not begin at the bridge but begins at the bridge's first downstream device. This will miss handling CXL protocol errors in a CXL root port. A separate CXL recovery is needed because of the different handling requirements Add a new function, cxl_do_recovery() using the following. Add cxl_walk_bridge() to iterate the detected error's sub-topology. cxl_walk_bridge() is similar to pci_walk_bridge() but the CXL flavor will begin iteration at the bridge rather than beginning at the bridge's first downstream child. Add cxl_report_error_detected() as an analog to report_error_detected(). It will call pci_driver::cxl_err_handlers for each iterated downstream child. The pci_driver::cxl_err_handlers UCE handler returns a boolean indicating if there was a UCE error detected during handling. cxl_do_recovery() uses the status from cxl_report_error_detected() to determine how to proceed. Non-fatal CXL UCE errors will be treated as fatal. If a UCE was present during handling then cxl_do_recovery() will kernel panic. Signed-off-by: Terry Bowman <terry.bowman@amd.com> --- drivers/pci/pci.h | 3 +++ drivers/pci/pcie/aer.c | 5 +++- drivers/pci/pcie/err.c | 54 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+), 1 deletion(-)