From patchwork Fri Oct 25 21:50:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Micha=C5=82_Winiarski?= X-Patchwork-Id: 13851869 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E80A120F3C9; Fri, 25 Oct 2024 21:51:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=192.198.163.9 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729893096; cv=fail; b=gcd14rnRRaL4v/EaELv9uWLLNJo1nAWwTzJ8VBsaB4zhCnSEPYv35DvssEh+u+6nHkXV9SvpeIFuBtMImOowsjmV0H1lwhlz4fh+VC3+0p3fIy7na79Ug+QpZXbTp41byMom47bCz1EmUWA2IS/X52u5mxQfudYsXSNSehxLpv8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729893096; c=relaxed/simple; bh=Cb21LiisF8elRGSHW71OF80D2cdzyNx82WHuMbx7zMQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=B54xzmNlwDo1MO+9ugJFjJbiS0U9ruQjifxN+oBJSw5mGfR0zn5zpWqqfiIABmk0JaLsaNyixDTIE1iySJK3HBSJO9ZmGDgf3i/cnwnB9L7sORUT+4b9sAmxEgO230XEcpvm3tKUj/VaLvMQB9MYBIObzPN5gELUMEaxSeljsUc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VUb3kU7q; arc=fail smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VUb3kU7q" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729893094; x=1761429094; h=from:to:cc:subject:date:message-id:in-reply-to: references:content-transfer-encoding:mime-version; bh=Cb21LiisF8elRGSHW71OF80D2cdzyNx82WHuMbx7zMQ=; b=VUb3kU7qZT0EbvnBaveU33qrqrX3EBi2OxBvMPCcB35X7W7blLcXz+2/ aWK615vrHyLc93Hmhp9TS0FRR6ySt3JSJfZM6oh1sxB9qTLMS/OeJMxFK vGYVCRWq4f1ovwP5Egr33qP8UYxr0M4wKg6vlfzUYGWQ4j9juMt/Daahm QWkb18SYuZbgBZeDL27fKiX9AU4SMusONV/16HKcLcfogYPd85EFM7kSO xT6KwxCXZyP0grQ9ZMjgR5bLyL40ABTBxNtoPCGMteni0Q90IYkf52/T2 m3JZ6laihH6BQUURLLFdxlkfHoDjWtkv30yqx+kDeBJQ60R5Nl/WZIkhy g==; X-CSE-ConnectionGUID: IWSPc1P6RUeYBoalVuqPaA== X-CSE-MsgGUID: ut6SNaExS+aHyogLdXQ8mg== X-IronPort-AV: E=McAfee;i="6700,10204,11236"; a="40192810" X-IronPort-AV: E=Sophos;i="6.11,233,1725346800"; d="scan'208";a="40192810" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 14:51:33 -0700 X-CSE-ConnectionGUID: 0tKz9vp2T/6CtIaXQkIZeQ== X-CSE-MsgGUID: SRzMFBBBT+OWfwNpzaBQKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,233,1725346800"; d="scan'208";a="104358193" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmviesa002.fm.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 25 Oct 2024 14:51:33 -0700 Received: from fmsmsx603.amr.corp.intel.com (10.18.126.83) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Oct 2024 14:51:32 -0700 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Fri, 25 Oct 2024 14:51:32 -0700 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (104.47.57.170) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 25 Oct 2024 14:51:32 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Tysue0GKSs8qWZ2J2pWbeGohRU3gzhCmexqocbxjhj/osK6VdZh104lLBnLiny1ITmXry7e0ij1GOOC9m2asb5ZOx+VLN5PyGvNePHA2/E5Dot86OroRQSFwUwwR8yFuxKtVSbKMzAqbhApDh2Si9Bi6ktoXmA44gyqkF1f+EJdERmccFJ0rOxLg7r7blG82Z8cenbGWDl+lRYSozTC14LSw2uH+2YMeG+OvuR6I9VgOHSW2iqnN7QI1XIOUIsxp60IlODyAalxr/mcUmKr4nWVPSw3VyJxe/3pV1t4ftml6WD6f1HNGRojs/d1UMs9ecrV1LXNFZKHjLbeFBSDfhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=prUTcacmshz3WO2AIjl4k3nUwsfAHpTcDq5xf2IXaoM=; b=oSoSEWKNhJU6L9JExtrcc3IWMYKw8x4w3JVdNAvxOU9t0BkDp9LYrxqfA9L4cnF/3nhnXZxJnOu95hSrrssrK4jePZHhdyKQdcXCdQrbf6gAFjmKsrfodHIZ5pKnuFNUBFZLyT2NCfRnN2Uj1V4hAhRljYUkQjEkL+oTcyVydEC8paaiDXZL9icWetl9NYBUIsqOfS1hus/p6a894IGCgGigGQspO5QIvQUJxtwraQLQof/OLz290EQReBCiPnWuQ367Z558wt9oIvjgK1LNtyLRthuGr10tGNoIDx+IIiJTEZDT1hLfraqU1auPb9fYk+/QGeyvoGSCBGPgiNrzSw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5373.namprd11.prod.outlook.com (2603:10b6:5:394::7) by CY8PR11MB7745.namprd11.prod.outlook.com (2603:10b6:930:90::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.16; Fri, 25 Oct 2024 21:51:25 +0000 Received: from DM4PR11MB5373.namprd11.prod.outlook.com ([fe80::927a:9c08:26f7:5b39]) by DM4PR11MB5373.namprd11.prod.outlook.com ([fe80::927a:9c08:26f7:5b39%5]) with mapi id 15.20.8093.018; Fri, 25 Oct 2024 21:51:25 +0000 From: =?utf-8?q?Micha=C5=82_Winiarski?= To: , , , , "Bjorn Helgaas" , =?utf-8?q?Christian_K=C3=B6nig?= , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , =?utf-8?q?Ilpo_J=C3=A4rvi?= =?utf-8?q?nen?= CC: Rodrigo Vivi , Michal Wajdeczko , Lucas De Marchi , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Matt Roper , =?utf-8?q?Micha=C5=82_Winiarski?= Subject: [PATCH v4 6/7] PCI: Allow drivers to control VF BAR size Date: Fri, 25 Oct 2024 23:50:37 +0200 Message-ID: <20241025215038.3125626-7-michal.winiarski@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241025215038.3125626-1-michal.winiarski@intel.com> References: <20241025215038.3125626-1-michal.winiarski@intel.com> X-ClientProxiedBy: WA1P291CA0007.POLP291.PROD.OUTLOOK.COM (2603:10a6:1d0:19::11) To DM4PR11MB5373.namprd11.prod.outlook.com (2603:10b6:5:394::7) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB5373:EE_|CY8PR11MB7745:EE_ X-MS-Office365-Filtering-Correlation-Id: f46ff9bf-6247-4a52-050f-08dcf53f2c21 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|366016|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?lsv79m2DZ3B69/WlJAtGseiesROQsMq?= =?utf-8?q?giqm1ao2dYx5b0jaWjQ0axHUbJ0smXS1bRZPG1Ao47MsBgNw43p/h0IdNDUFBmwM3?= =?utf-8?q?YN5h2BxjsF6nee/IjdparoOMPOCJwdQ4dLQja+6hiJGnuUstEz/aoykdLq5vrG6b3?= =?utf-8?q?K5Fzo9LK5b/rrGQIYORKuUI7h7VhuQoNzzFjz5SfEg3pFtNZWTaidVUi4LMTKVEJa?= =?utf-8?q?YIkv8gT14h1ME0rF2XarAYZ3l8RDchECESJk1cFfjOlEkNozzaDPIqBttknLCkh8e?= =?utf-8?q?eP1cQNcWFfPSwqR0QXqHGkjY0eJrV3iF6t8hMjRlJ9WVqn82QOvqcSc+dAlFVmBmX?= =?utf-8?q?lHbtftF7mWwOLgyZGpVdxY65xCHgT+KA9KNjJD3bjKXyeeKbxxI6cbWGfJKz7zNU5?= =?utf-8?q?kCTzPU+O61NQT0oQ4Dan3EYl4uSwSZDrzbJNJtBuK4hAoQnlg3BEVVH7Z1aeUusi2?= =?utf-8?q?y5HPtVIA1se4YfJmVGZu5ffPWWLVw/jHPPddmS9cp7veNCtjAxDtpZpR05/AXmBlT?= =?utf-8?q?cOSLjlHg/rGvfvdHbSNFPVIPIH219ZSUlIyHyPhxCI+JBvpblJsZiFsI4CmexMTWL?= =?utf-8?q?FTBqHVdx3deuifFSOjH7wR6rX2hJXS2MwyOPPKCc+U3t/ovTKELsKysn4zvx742ec?= =?utf-8?q?Gq45wd2omwb2j6yc20n09owgIvl2IEEgMPLoXHXqVAhBisw6amTlj/tRcE8RVwd58?= =?utf-8?q?K4WGDtImN2EDxIBRxQdLurJoUKfHZY0wpOVvtwJfttZWmel+Ic2OkQjqY+kx+u1pD?= =?utf-8?q?30sHojKAWEyBqF4fBEeryaWtQvxF2EGTvzsumD0p7GUIspXD2fkLu3uVfvIL35BFF?= =?utf-8?q?PdmQs1oYir/1BhaPaQ/g8ER5iYuOvx6wJ/XhnDBQA0/gUVuMH8wfjLl+l0FZxsq0B?= =?utf-8?q?eoffTYbgrC10Zt+jv7+hVxfQnB5Lue+0R+R4mEwizhwr6b8xSECJdC6xiXWHLOdQt?= =?utf-8?q?pw8xCZ2Kc2mKKHynDhwr2RJyOO3pqcbn6Lxfv14xPG/+9B/834xC9GeI2Vfvechgg?= =?utf-8?q?sqFsyjM6KJz4Uyfa8nRyPmnQOcL972/MmFdzXiJNXIJ23SkcOnCK4TauDdBU0+WTX?= =?utf-8?q?iYTgh/fBQ8fjp3nRnmtcJGMwSZg78clEEDWyZ+DKyecb6fMRcMmYi8fTYZA9RS/0K?= =?utf-8?q?fGR6PFh7N44H/VtgZwrIC5vXq9lZ8mPup/T7mz5fPAzKVz7UVRBYAaGNZ5aJFJaQH?= =?utf-8?q?H1Q4pYsoJ+8IUloe8bZEmKbGET89giW1GuTlMJNkmWdH0dGYMvg2hMAEHPXDPx9U+?= =?utf-8?q?fX9xHtmyZ7lr3?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM4PR11MB5373.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(7416014)(366016)(1800799024)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?+UvLrwKUsQ+ltBLKefJZrGmnd7pq?= =?utf-8?q?s+ur43kvM9npmtOEYdJHxPhzEYSiQS4Emsq7O7DINOmGKTtBTxNvXGYQJtqT8PMle?= =?utf-8?q?xtnNbdcOMwU5m4gheO+zK1nvXaMmbF8/i+IPxBg/gL8i63hWrEr639+6M+It4uCzT?= =?utf-8?q?mF1CumcfZm76hlmPNTKaNhx1nJFZpeMgvpuzCXkXMIOIV5E8QETQLVl3iG2c4WuUp?= =?utf-8?q?z0glKXXq4Epu+mbm7GPp/Oe5lD8+rbTQ37kTBjQ5mIg38hvotJ//ZpghN4Rej1DGI?= =?utf-8?q?A0kFpmSTfeoqUE26l3d7xwJKE5SFiNQAd14WEE8JtPHYryP6UedjoF28zeDhZfRLN?= =?utf-8?q?HWHymrHRNcHBSpTlrVL+k7Us4zTKzBfF3SwkZACwBIC7wuwB+nJqSwyiHLnTr0raw?= =?utf-8?q?de4Y1t6acr185+ciORHLW+AJOLi99NIz3Gt9rB6qOelF7FNwdF+sQ6UPN1d9tbctS?= =?utf-8?q?/5AGPuHr84QBdhbvEdxeu96RqXQPga68mIiAJ8ReBGsHpqtIPuQmpN1+lZtQsC7el?= =?utf-8?q?IjEuO3XHsJ2CEf2jCgua29U6xxolQHyA2w0mkUGe+7m//Bxvn5ocRUKIz2iu6iN1/?= =?utf-8?q?DVlGOL0L0HRgqdyQjcvdKNacx9x3Zt4wgE+wu0s7PnTRfRmR3ELtBYcE6x8ZtfXI0?= =?utf-8?q?l+uXdIdR/DoLpvSzhgoSHMYM4ZO9ztJwsyf0qNtSbtrXADoOdu6rWAdRG0wJMUbmP?= =?utf-8?q?DNDokQVEZE8KWBZ5ET0qjMqaiHXaTBLkRM+SXcPzfKDgz4MLehtHGIwnYG7Tcp5cY?= =?utf-8?q?7bUv1HYvJUW4WcLYVa0hN3w/pziaIwy0sPJD0T7mf0qcDekeE3+ny0EGrR/n9cc98?= =?utf-8?q?rhNLWkXdtAeyXzdkKlT9PUGjjdmHI0YS2598NGf6IJZTTqFZp6ij8ES5GvolMM3Vh?= =?utf-8?q?jgpb97sXD1nPfckJ560mU2crmcUUVH5v2+ZcmqkIpTiiqtlG2CHFo+QD28G1upaUJ?= =?utf-8?q?sFHiA8h74+zW30UOF3NDax3RSJ6b87r62oYI8zPt+mO4g5AsjapY1/L5Z8yVvdreA?= =?utf-8?q?mQsKwQxic+BCaMuWouf2QmFmul4xfn1VMBD+0/OWI83gSPNz2hXu57sAYyj5K79C3?= =?utf-8?q?Cgvw5OfV2/UEUJsX6Ieaxpy30C4EYx0fvH0c4uhZT67CUpcRQO6rIzDtIFJx44anv?= =?utf-8?q?G8C0Y8DMQrDQJ4/M73yXJXdE7LaDv/9ZqGLMmDyEs+NLelpqF/B4L1eZUeQvboy9+?= =?utf-8?q?NG1clP1ko6OYgnf2wDSNzAJfk8VUwkEyPIYPDW/vO8AB6jx2esuou0gwDRDSqaE7o?= =?utf-8?q?pS9BIk0Jrb/Laphci59O/FZF24ibujoon8U6GFwg+WZBjocplbX6WYhUfubsrltqv?= =?utf-8?q?Ar6opUBFUlI8E6Ws3DgvF3wgnNqqXZXiQ1QjIRmcyQSnTO0tkSq3uO8jHd6cNh69m?= =?utf-8?q?Erw41mOKlVF4JqEA5zDSB3vS6MwIGkktsF7w+DlrpTc5ErAINhYSLP10+qgzry7hR?= =?utf-8?q?HA+6iNyH66sIpNDb11pazhmloB4ioWlbVqXirbJnWyszUqvpM0o0RYlEOIrjTNKyM?= =?utf-8?q?Wi3hVCa2Q3ezah4MRBMIxnXRFsMygnzfYA=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: f46ff9bf-6247-4a52-050f-08dcf53f2c21 X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB5373.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:51:25.4462 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4lpjpm+PrdnrSLgXcW4jGDb0w+DsQi3EgAsRb5u1vRJuEndwQGxDvdcDYaVjWSkRjNvPcctCIxHPjzPBcklHxE8iTTcqRY2+O9FG4uubvCg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR11MB7745 X-OriginatorOrg: intel.com Drivers could leverage the fact that the VF BAR MMIO reservation is created for total number of VFs supported by the device by resizing the BAR to larger size when smaller number of VFs is enabled. Add a pci_iov_vf_bar_set_size() function to control the size and a pci_iov_vf_bar_get_sizes() helper to get the VF BAR sizes that will allow up to num_vfs to be successfully enabled with the current underlying reservation size. Signed-off-by: MichaƂ Winiarski --- drivers/pci/iov.c | 80 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 6 ++++ 2 files changed, 86 insertions(+) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 5de828e5a26ea..de8d473459440 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -1281,3 +1281,83 @@ int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn) return nr_virtfn; } EXPORT_SYMBOL_GPL(pci_sriov_configure_simple); + +/** + * pci_iov_vf_bar_set_size - set a new size for a VF BAR + * @dev: the PCI device + * @resno: the resource number + * @size: new size as defined in the spec (0=1MB, 19=512GB) + * + * Set the new size of a VF BAR that supports VF resizable BAR capability. + * Unlike pci_resize_resource(), this does not cause the resource that + * reserves the MMIO space (originally up to total_VFs) to be resized, which + * means that following calls to pci_enable_sriov() can fail if the resources + * no longer fit. + * + * Returns 0 on success, or negative on failure. + * + */ +int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size) +{ + int ret; + u32 sizes; + + if (!pci_resource_is_iov(resno)) + return -EINVAL; + + if (pci_iov_is_memory_decoding_enabled(dev)) + return -EBUSY; + + sizes = pci_rebar_get_possible_sizes(dev, resno); + if (!sizes) + return -ENOTSUPP; + + if (!(sizes & BIT(size))) + return -EINVAL; + + ret = pci_rebar_set_size(dev, resno, size); + if (ret) + return ret; + + pci_iov_resource_set_size(dev, resno, pci_rebar_size_to_bytes(size)); + + return 0; +} +EXPORT_SYMBOL_GPL(pci_iov_vf_bar_set_size); + +/** + * pci_iov_vf_bar_get_sizes - get VF BAR sizes that allow to create up to num_vfs + * @dev: the PCI device + * @resno: the resource number + * @num_vfs: number of VFs + * + * Get the sizes of a VF resizable BAR that can fit up to num_vfs within the + * resource that reserves the MMIO space (originally up to total_VFs) the as + * bitmask defined in the spec (bit 0=1MB, bit 19=512GB). + * + * Returns 0 if BAR isn't resizable. + * + */ +u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs) +{ + resource_size_t size; + u32 sizes; + int i; + + sizes = pci_rebar_get_possible_sizes(dev, resno); + if (!sizes) + return 0; + + while (sizes > 0) { + i = __fls(sizes); + size = pci_rebar_size_to_bytes(i); + + if (size * num_vfs <= pci_resource_len(dev, resno)) + break; + + sizes &= ~BIT(i); + } + + return sizes; +} +EXPORT_SYMBOL_GPL(pci_iov_vf_bar_get_sizes); diff --git a/include/linux/pci.h b/include/linux/pci.h index 573b4c4c2be61..1b9e7e3cab0ce 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2371,6 +2371,8 @@ int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); int pci_sriov_get_totalvfs(struct pci_dev *dev); int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); +int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size); +u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs); void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); /* Arch may override these (weak) */ @@ -2423,6 +2425,10 @@ static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) #define pci_sriov_configure_simple NULL static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) { return 0; } +static inline int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size) +{ return -ENODEV; } +static inline u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs) +{ return 0; } static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } #endif