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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?x+q5TMiSUm57Rwb+6LD/LTnaT5qZ?= =?utf-8?q?nj1Zus4/nuCEVsbhwEffNjfrJS0BTnUqtH4jYj/ucSOg/qj4R8vikF+5BzVsAQvLC?= =?utf-8?q?zbNyCpIa9NdJot/L9faZAjUCCAvGClPbB4GkjdNzFqLduRGev/u4yGmXiOYd7aYAr?= =?utf-8?q?XVDONVcnN/OyDO9pbPvOUrPIGrU8dIwBr3wxysRrkzaDuvyF+Ym3MtTHTVC+rriXq?= =?utf-8?q?m6Rb2kSeTVuR/S+Et3H/68PNoaA9tOqP4HVSUtTWFrYjZRPLXqsS+Liu1A19yblYH?= =?utf-8?q?FfwzjHmtvFxs8G73RsuXnjWh+Mpp/EoHhmlrJe5vKl0IzX3KW6noFc6zUsLE2gzgc?= =?utf-8?q?dqpgX2ryhzcXzkoM43Z8XN/l+sqANt4fX9Oty9swHtHmvcKoYv5vxlUvWTJaJwzHH?= =?utf-8?q?6wwyGI53S9ze+/nv9zT8sospRqgX+bffVOb9mdlP2FyuuFXS/+NnLGwsvIrZcwHHc?= =?utf-8?q?zhuIdDOrc4sX+4zSmOMRMk7ux3zgrxhPAnA4mIG+KtzD4mH0CFCTtTzYd/TrvovWo?= =?utf-8?q?UwgqVOatPOqfPXhN7GK/mFv7Y7XScD352affa9ao7ZfYPo5oST+5QpmAReb92XxDJ?= =?utf-8?q?a83VvKLE+z2pm7ELeh8VAEMo55zdxZxUwLdUPnx3mGErdmuPpirt8ieoQRszJyAAC?= =?utf-8?q?H6srrqhaeR7MA0NV0WV+Jmff/R+dPxYzCJIfGqHdop0zEBgZdmyKVDq4ZXa5bqQW9?= =?utf-8?q?LAa4xA29y3E1qjogZoiSCyHt8xZBwjl5ZgPAGS0k7QzhzvMaUS7xi5l/2aekSAm96?= =?utf-8?q?lxMoqxBiOuXv8VEGXLpg4xpspeXfOcl+SOptzJZVxG19hkvor6qiLBGVCrvSTvgco?= =?utf-8?q?vU3fc0U4QG74cEVmdCV7XPrO5uW5PdDNnpNYKYWf4pmeW2yB8WA7S3aARdK1VRgsU?= =?utf-8?q?+dWSsVnJWjoniVlB6DJkgYB4w7+8Mkm+EI4Fu6M6aWMkEv/qEpCx5nQbMlz2G7axp?= =?utf-8?q?5i74GWlfk6tfav5bpwq9YDIIbG1ZzhgL3dMQIA/OmfiSlUPZo6awEeHTFJDn6U+bG?= =?utf-8?q?WqSAr3pci5mheFpujhwphtuKGj1MGpVFhrLrP1WWO8psBEajod2KzQ3VrpMxn1ZRn?= =?utf-8?q?JZvFtPKVaeugx5s7FKFWubF8eQW57L4km3nNi725Gxz/Y+la09mAv9dzrSt6cych3?= =?utf-8?q?/0LTcGJlcHZ47+pNT3ZgWRVmPucLtAj9BeTyUsnnmKEWYEQh40E3ErZ4TQGxBrBAU?= =?utf-8?q?3Zodqb2JGtMozqRduX8sR8l2+QOnH1Vvx2/lXAMSDCyrux0cXBQt1P71YvigDgf2A?= =?utf-8?q?i3wUjPc/B8HPcPDmLUBZxz0r9lHmc9OXNkyxhyGg1KUrPaPk1my1MxiqNkWiisKfc?= =?utf-8?q?C2TWaQ1yBIkbLh/54nakzyRhhYCuL9YwLHLGwrxw99haPK73HCsCrlz65/9B8O1ub?= =?utf-8?q?e7PoLOI/2oThmhNC4A6nTwMZJvG1UK8fbdpHuaAzh+aQGlluy+yat03d4/0nW+UE9?= =?utf-8?q?i0sbG3m6xiWy4G+l5IaAjNK6F8BqkxnFu4Ms+FuD0lmel154zW5okW74=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 046d74c5-dff2-4cef-a043-08dcfab8de10 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Nov 2024 21:05:08.7214 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mlT5jYTeV9wNh7HYtxZ/nlVedKSn8gVaW9HWKNkgex/IjGqC2QMmKBli8wuPbxZurbbaqznYbNl/lM5+gc0AdQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA1PR04MB10502 For the i.MX95, configuration of a LUT is necessary to convert Bus Device Function (BDF) to stream IDs, which are utilized by both IOMMU and ITS. This involves examining the msi-map and smmu-map to ensure consistent mapping of PCI BDF to the same stream IDs. Subsequently, LUT-related registers are configured. In the absence of an msi-map, the built-in MSI controller is utilized as a fallback. Additionally, register a PCI bus callback function enable_device() and disable_device() to config LUT when enable a new PCI device. Signed-off-by: Frank Li Acked-by: Richard Zhu --- Change from v3 to v4 - Check target value at of_map_id(). - of_node_put() for target. - add case for msi-map exist, but rid entry is not exist. Change from v2 to v3 - Use the "target" argument of of_map_id() - Check if rid already in lut table when enable device change from v1 to v2 - set callback to pci_host_bridge instead pci->ops. --- drivers/pci/controller/dwc/pci-imx6.c | 177 +++++++++++++++++++++++++++++++++- 1 file changed, 176 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 94f3411352bf0..1be17bc39ce54 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -55,6 +55,22 @@ #define IMX95_PE0_GEN_CTRL_3 0x1058 #define IMX95_PCIE_LTSSM_EN BIT(0) +#define IMX95_PE0_LUT_ACSCTRL 0x1008 +#define IMX95_PEO_LUT_RWA BIT(16) +#define IMX95_PE0_LUT_ENLOC GENMASK(4, 0) + +#define IMX95_PE0_LUT_DATA1 0x100c +#define IMX95_PE0_LUT_VLD BIT(31) +#define IMX95_PE0_LUT_DAC_ID GENMASK(10, 8) +#define IMX95_PE0_LUT_STREAM_ID GENMASK(5, 0) + +#define IMX95_PE0_LUT_DATA2 0x1010 +#define IMX95_PE0_LUT_REQID GENMASK(31, 16) +#define IMX95_PE0_LUT_MASK GENMASK(15, 0) + +#define IMX95_SID_MASK GENMASK(5, 0) +#define IMX95_MAX_LUT 32 + #define to_imx_pcie(x) dev_get_drvdata((x)->dev) enum imx_pcie_variants { @@ -82,6 +98,7 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) +#define IMX_PCIE_FLAG_HAS_LUT BIT(8) #define imx_check_flag(pci, val) (pci->drvdata->flags & val) @@ -134,6 +151,7 @@ struct imx_pcie { struct device *pd_pcie_phy; struct phy *phy; const struct imx_pcie_drvdata *drvdata; + struct mutex lock; }; /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ @@ -925,6 +943,155 @@ static void imx_pcie_stop_link(struct dw_pcie *pci) imx_pcie_ltssm_disable(dev); } +static int imx_pcie_add_lut(struct imx_pcie *imx_pcie, u16 reqid, u8 sid) +{ + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + u32 data1, data2; + int i; + + if (sid >= 64) { + dev_err(dev, "Invalid SID for index %d\n", sid); + return -EINVAL; + } + + guard(mutex)(&imx_pcie->lock); + + for (i = 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); + + if (!(data1 & IMX95_PE0_LUT_VLD)) + continue; + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + + /* Needn't add duplicated Request ID */ + if (reqid == FIELD_GET(IMX95_PE0_LUT_REQID, data2)) + return 0; + } + + for (i = 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); + if (data1 & IMX95_PE0_LUT_VLD) + continue; + + data1 = FIELD_PREP(IMX95_PE0_LUT_DAC_ID, 0); + data1 |= FIELD_PREP(IMX95_PE0_LUT_STREAM_ID, sid); + data1 |= IMX95_PE0_LUT_VLD; + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); + + data2 = 0xffff; + data2 |= FIELD_PREP(IMX95_PE0_LUT_REQID, reqid); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); + + return 0; + } + + dev_err(dev, "All lut already used\n"); + return -EINVAL; +} + +static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 reqid) +{ + u32 data2 = 0; + int i; + + guard(mutex)(&imx_pcie->lock); + + for (i = 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + if (FIELD_GET(IMX95_PE0_LUT_REQID, data2) == reqid) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); + + break; + } + } +} + +static int imx_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) +{ + u32 sid_i = 0, sid_m = 0, rid = pci_dev_id(pdev); + struct device_node *target; + struct imx_pcie *imx_pcie; + struct device *dev; + int err_i, err_m; + + imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); + dev = imx_pcie->pci->dev; + + target = NULL; + err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", &target, &sid_i); + if (target) + of_node_put(target); + else + err_i = -EINVAL; + + target = NULL; + err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", &target, &sid_m); + + /* + * Return failure if msi-map exist and no entry for rid because dwc common + * driver will skip setting up built-in MSI controller if msi-map existed. + * + * err_m target + * 0 NULL Return failure, function not work. + * !0 NULL msi-map not exist, use built-in MSI. + * 0 !NULL Find one entry. + * !0 !NULL Invalidate case. + */ + if (!err_m && !target) + return -EINVAL; + else if (target) + of_node_put(target); /* Find entry for rid in msi-map */ + + /* + * msi-map iommu-map + * Y Y ITS + SMMU, require the same sid + * Y N ITS + * N Y DWC MSI Ctrl + SMMU + * N N DWC MSI Ctrl + */ + if (!err_i && !err_m) + if ((sid_i & IMX95_SID_MASK) != (sid_m & IMX95_SID_MASK)) { + dev_err(dev, "its and iommu stream id miss match, please check dts file\n"); + return -EINVAL; + } + + /* + * Both iommu-map and msi-map not exist, use dwc built-in MSI + * controller, do nothing here. + */ + if (err_i && err_m) + return 0; + + if (!err_i) + return imx_pcie_add_lut(imx_pcie, rid, sid_i); + else if (!err_m) + /* Hardware auto add 2 bit controller id ahead of stream ID */ + return imx_pcie_add_lut(imx_pcie, rid, sid_m & IMX95_SID_MASK); + + return 0; +} + +static void imx_pcie_disable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) +{ + struct imx_pcie *imx_pcie; + + imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); + imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); +} + static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -941,6 +1108,11 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) } } + if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { + pp->bridge->enable_device = imx_pcie_enable_device; + pp->bridge->disable_device = imx_pcie_disable_device; + } + imx_pcie_assert_core_reset(imx_pcie); if (imx_pcie->drvdata->init_phy) @@ -1292,6 +1464,8 @@ static int imx_pcie_probe(struct platform_device *pdev) imx_pcie->pci = pci; imx_pcie->drvdata = of_device_get_match_data(dev); + mutex_init(&imx_pcie->lock); + /* Find the PHY if one is defined, only imx7d uses it */ np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); if (np) { @@ -1587,7 +1761,8 @@ static const struct imx_pcie_drvdata drvdata[] = { }, [IMX95] = { .variant = IMX95, - .flags = IMX_PCIE_FLAG_HAS_SERDES, + .flags = IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_HAS_LUT, .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), .ltssm_off = IMX95_PE0_GEN_CTRL_3,