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Fri, 15 Nov 2024 10:30:45 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 15 Nov 2024 02:30:41 -0800 From: Krishna chaitanya chundru Date: Fri, 15 Nov 2024 16:00:23 +0530 Subject: [PATCH v4 3/3] PCI: qcom: Update ICC and OPP values during link up event Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241115-remove_wait1-v4-3-7e3412756e3d@quicinc.com> References: <20241115-remove_wait1-v4-0-7e3412756e3d@quicinc.com> In-Reply-To: <20241115-remove_wait1-v4-0-7e3412756e3d@quicinc.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Konrad Dybcio CC: , , , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , , , , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731666627; l=1234; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=SMJJgYPH0VoGR55VneQNmLBv8TSMazn2Q6TLDzZHqrU=; b=9intVnxYhFLrDZboWXaLPVdNry23wIwyis3ZH/sI8B8nwj3bvkQJAmkSnV44VxTkBr+a+dX4r ByXyDLe4gyrDt5kHHhKt1oZdWY7nGS1V0YVL5Bbd4PtUg9nKqmBoorK X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: mj43ACRTjM06U-6ORqlC0OB-d6GzWrZV X-Proofpoint-ORIG-GUID: mj43ACRTjM06U-6ORqlC0OB-d6GzWrZV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=963 bulkscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411150089 As the wait for linkup is removed if there is a global IRQ support, there is no guarantee that the correct icc and opp votes are updated as part of probe. And also global IRQ is being used as hotplug event in case link hasn't come up as part probe, link up IRQ is the correct place to update the ICC and OPP votes. So, as part of the PCIe link up event, update ICC and OPP values. Fixes: 4581403f6792 ("PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt") Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index c39d1c55b50e..39f5c782e2c3 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1558,6 +1558,8 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) pci_lock_rescan_remove(); pci_rescan_bus(pp->bridge->bus); pci_unlock_rescan_remove(); + + qcom_pcie_icc_opp_update(pcie); } else { dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", status);