From patchwork Wed Dec 4 11:33:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13893605 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C6201B3929; Wed, 4 Dec 2024 11:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733312073; cv=none; b=HGDXld1mI5z1maxoOg6DfOkhSrqgVS1VO+CrppL4K2h7V3ZmZoI9SjBkN2zIaDCryDf9JguiechQyfwxwPA2MfVO5SHII2dqRdsHkxe8tdLd/MRXMLP2yt8U9sSNy+J1MwVc8BG/BP6IvxS1AdQ3cJ+asd9oAmqxYJYlbwNcf5I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733312073; c=relaxed/simple; bh=Ax3XDc05AXTL8/YLOuz61tnW5PC9OBV1gPdZI7L/GXk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JS9PpezsZH4+SUTWWmsezy5Bt4V9MFuIKMprmIDvQxz9lQ+qVrlKztsB9n4qFaoMNy/Yep/usvNMxyBl4PBq3cwJl8ohOFeCwoUMCcqZ9HvWIRiYcE5RuQBsQzBHvlsLZ0azjZKBCoifu1swq0d+8IJeHtF3p11q8r7cd7v15mI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=RdRAT8Sw; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="RdRAT8Sw" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B43juP3020113; Wed, 4 Dec 2024 11:34:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wX57069OFQvWJ6I4NwMeCQjFwNM0/PlY6V1BTsO8HVM=; b=RdRAT8SwUp/3wXcF ZSod+vY525YJqiDIQPA88sQkzxL70uoyPdgiwZ4sjAGaUljhROw8JxgzBv4Lg3nq PrNdOPcxtcwlTqUVzceXL5JoBfFTwnjQT5XBt4OBSrviV95S0dANu/I80spc0aRy mNMeFjlkeW6MZkmo0qinGn1Rn3cuQCqcF+SV0jLs6ID6p00oJRhtW8KhzO0lA+BN AfQMJxl0hLDFTAAuE9G3qsQX+QJYyGgAQkmKzrsW1LK3dWZ+uxXzuDbl1/9+zwwW d/g85qlrw83xg67+M4yx9Dss/ICnZkrrA1FbPE9ZbYamaImsF+VlUDutPSnY4OmK eYNhYA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43a3exb0a7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Dec 2024 11:34:23 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B4BYMwp013671 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Dec 2024 11:34:22 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Dec 2024 03:34:16 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , CC: Praveenkumar I Subject: [PATCH v2 3/6] dt-bindings: PCI: qcom: Add IPQ5332 SoC Date: Wed, 4 Dec 2024 17:03:26 +0530 Message-ID: <20241204113329.3195627-4-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204113329.3195627-1-quic_varada@quicinc.com> References: <20241204113329.3195627-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: UMbHZzvOR44I5cK7t0OOftjD2isQoyPo X-Proofpoint-GUID: UMbHZzvOR44I5cK7t0OOftjD2isQoyPo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=961 clxscore=1015 phishscore=0 adultscore=0 suspectscore=0 malwarescore=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040090 From: Praveenkumar I Add support for the PCIe controller on the Qualcomm IPQ5332 SoC to the bindings. Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- v2: Use ipq9574 clock & reset details instead of a new one for ipq5332 --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index bd87f6b49d68..a7c5d0ce7de8 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -163,6 +164,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 - qcom,pcie-ipq9574 @@ -407,6 +409,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq9574 then: properties: @@ -555,6 +558,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074