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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF0000231A.mail.protection.outlook.com (10.167.242.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8398.14 via Frontend Transport; Sat, 8 Feb 2025 00:29:59 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 7 Feb 2025 18:29:57 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 01/17] PCI/AER: Introduce 'struct cxl_err_handlers' and add to 'struct pci_driver' Date: Fri, 7 Feb 2025 18:29:25 -0600 Message-ID: <20250208002941.4135321-2-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250208002941.4135321-1-terry.bowman@amd.com> References: <20250208002941.4135321-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231A:EE_|IA1PR12MB7520:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a5cd6b6-4dc3-4807-8038-08dd47d7b871 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|36860700013|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2025 00:29:59.2902 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a5cd6b6-4dc3-4807-8038-08dd47d7b871 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7520 CXL.io is implemented on top of PCIe Protocol Errors. But, CXL.io and PCIe have different handling requirements for uncorrectable errors (UCE). The PCIe AER service driver may attempt recovering PCIe devices with UCE while recovery is not used for CXL.io. Recovery is not used in the CXL.io case because of potential corruption on what can be system memory. Create pci_driver::cxl_err_handlers structure similar to pci_driver::error_handler. Create handlers for correctable and uncorrectable CXL.io error handling. The CXL error handlers will be used in future patches adding CXL PCIe Port Protocol Error handling. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Fan Ni Reviewed-by: Ira Weiny Reviewed-by: Gregory Price --- include/linux/pci.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 47b31ad724fa..1d62e785ae1f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -884,6 +884,14 @@ struct pci_error_handlers { void (*cor_error_detected)(struct pci_dev *dev); }; +/* Compute Express Link (CXL) bus error event callbacks */ +struct cxl_error_handlers { + /* CXL bus error detected on this device */ + pci_ers_result_t (*error_detected)(struct pci_dev *dev); + + /* Allow device driver to record more details of a correctable error */ + void (*cor_error_detected)(struct pci_dev *dev); +}; struct module; @@ -929,6 +937,7 @@ struct module; * @sriov_get_vf_total_msix: PF driver callback to get the total number of * MSI-X vectors available for distribution to the VFs. * @err_handler: See Documentation/PCI/pci-error-recovery.rst + * @cxl_err_handler: Compute Express Link specific error handlers. * @groups: Sysfs attribute groups. * @dev_groups: Attributes attached to the device that will be * created once it is bound to the driver. @@ -954,6 +963,7 @@ struct pci_driver { int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); const struct pci_error_handlers *err_handler; + const struct cxl_error_handlers *cxl_err_handler; const struct attribute_group **groups; const struct attribute_group **dev_groups; struct device_driver driver;