| Message ID | 20250210-preset_v6-v6-1-cbd837d0028d@oss.qualcomm.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | PCI: dwc: Add support for configuring lane equalization presets | expand |
On 10.02.2025 8:30 AM, Krishna Chaitanya Chundru wrote: > Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data > rates used in lane equalization procedure. > > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> > --- > This patch depends on the this dt binding pull request which got recently > merged: https://github.com/devicetree-org/dt-schema/pull/146 > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
On Mon, Feb 10, 2025 at 01:00:00PM +0530, Krishna Chaitanya Chundru wrote: > Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data > rates used in lane equalization procedure. > > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> > --- > This patch depends on the this dt binding pull request which got recently > merged: https://github.com/devicetree-org/dt-schema/pull/146 > --- > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 4936fa5b98ff..1b815d4eed5c 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > phys = <&pcie3_phy>; > phy-names = "pciephy"; > > + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>, > + /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; Why 2 16bit arrays? - Mani
On 2/14/2025 2:14 PM, Manivannan Sadhasivam wrote: > On Mon, Feb 10, 2025 at 01:00:00PM +0530, Krishna Chaitanya Chundru wrote: >> Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data >> rates used in lane equalization procedure. >> >> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> >> --- >> This patch depends on the this dt binding pull request which got recently >> merged: https://github.com/devicetree-org/dt-schema/pull/146 >> --- >> --- >> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++ >> 1 file changed, 13 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> index 4936fa5b98ff..1b815d4eed5c 100644 >> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> phys = <&pcie3_phy>; >> phy-names = "pciephy"; >> >> + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>, >> + /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; > > Why 2 16bit arrays? > Just to keep line length below 100, if I use single line it is crossing 100 lines. - Krishna Chaitanya. > - Mani >
On 14.02.2025 9:48 AM, Krishna Chaitanya Chundru wrote: > > > On 2/14/2025 2:14 PM, Manivannan Sadhasivam wrote: >> On Mon, Feb 10, 2025 at 01:00:00PM +0530, Krishna Chaitanya Chundru wrote: >>> Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data >>> rates used in lane equalization procedure. >>> >>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> >>> --- >>> This patch depends on the this dt binding pull request which got recently >>> merged: https://github.com/devicetree-org/dt-schema/pull/146 >>> --- >>> --- >>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++ >>> 1 file changed, 13 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> index 4936fa5b98ff..1b815d4eed5c 100644 >>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >>> phys = <&pcie3_phy>; >>> phy-names = "pciephy"; >>> + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>, >>> + /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; >> >> Why 2 16bit arrays? >> > Just to keep line length below 100, if I use single line it is crossing > 100 lines. Oh I didn't notice this.. Ideally we would have <A0>, <A1>, ..., <An>; But it seems like /bits/ applies individually to each entry? That's a bit weird, but I'll add it to my list of things I don't like about dtc.. Let's do: eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555>; for now Konrad
On Fri, Feb 14, 2025 at 02:18:48PM +0530, Krishna Chaitanya Chundru wrote: > > > On 2/14/2025 2:14 PM, Manivannan Sadhasivam wrote: > > On Mon, Feb 10, 2025 at 01:00:00PM +0530, Krishna Chaitanya Chundru wrote: > > > Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data > > > rates used in lane equalization procedure. > > > > > > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> > > > --- > > > This patch depends on the this dt binding pull request which got recently > > > merged: https://github.com/devicetree-org/dt-schema/pull/146 > > > --- > > > --- > > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++ > > > 1 file changed, 13 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > > index 4936fa5b98ff..1b815d4eed5c 100644 > > > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > > @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > > > phys = <&pcie3_phy>; > > > phy-names = "pciephy"; > > > + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>, > > > + /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; > > > > Why 2 16bit arrays? > > > Just to keep line length below 100, if I use single line it is crossing > 100 lines. > You *should* keep it as a single array even if it crosses 100 column width. - Mani
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 4936fa5b98ff..1b815d4eed5c 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie3_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>, + /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + operating-points-v2 = <&pcie3_opp_table>; status = "disabled"; @@ -3411,6 +3416,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie6a_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + status = "disabled"; }; @@ -3538,6 +3547,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie5_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; }; @@ -3662,6 +3673,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie4_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; pcie4_port0: pcie@0 {
Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data rates used in lane equalization procedure. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> --- This patch depends on the this dt binding pull request which got recently merged: https://github.com/devicetree-org/dt-schema/pull/146 --- --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)