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client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BL6PEPF00020E66.mail.protection.outlook.com (10.167.249.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8445.10 via Frontend Transport; Tue, 11 Feb 2025 08:17:38 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 11 Feb 2025 02:17:36 -0600 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Tue, 11 Feb 2025 02:17:33 -0600 From: Thippeswamy Havalige To: , , , , , , CC: , , , , , Thippeswamy Havalige Subject: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controller Date: Tue, 11 Feb 2025 13:47:24 +0530 Message-ID: <20250211081724.320279-3-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250211081724.320279-1-thippeswamy.havalige@amd.com> References: <20250211081724.320279-1-thippeswamy.havalige@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: thippeswamy.havalige@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E66:EE_|DM4PR12MB7549:EE_ X-MS-Office365-Filtering-Correlation-Id: 64422522-f108-4719-d5cd-08dd4a748c01 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700013|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 08:17:38.1289 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64422522-f108-4719-d5cd-08dd4a748c01 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7549 The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices incorporate the Coherency and PCIe Gen5 Module, specifically the Next-Generation Compact Module (CPM5NC). The integrated CPM5NC block, along with the built-in bridge, can function as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer rates of up to 32 GT/s, capable of supporting up to a x16 lane-width configuration. Bridge errors are managed using a specific interrupt line designed for CPM5N. Legacy interrupt support is not available. Currently in this patch Bridge errors support is not added. Signed-off-by: Thippeswamy Havalige --- drivers/pci/controller/pcie-xilinx-cpm.c | 85 ++++++++++++++---------- 1 file changed, 51 insertions(+), 34 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c index 81e8bfae53d0..c26ba662efd7 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -84,6 +84,7 @@ enum xilinx_cpm_version { CPM, CPM5, CPM5_HOST1, + CPM5NC_HOST, }; /** @@ -483,31 +484,33 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) else dev_info(port->dev, "PCIe Link is DOWN\n"); - /* Disable all interrupts */ - pcie_write(port, ~XILINX_CPM_PCIE_IDR_ALL_MASK, - XILINX_CPM_PCIE_REG_IMR); - - /* Clear pending interrupts */ - pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_IDR) & - XILINX_CPM_PCIE_IMR_ALL_MASK, - XILINX_CPM_PCIE_REG_IDR); - - /* - * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to - * CPM SLCR block. - */ - writel(variant->ir_misc_value, - port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); + if (variant->version != CPM5NC_HOST) { + /* Disable all interrupts */ + pcie_write(port, ~XILINX_CPM_PCIE_IDR_ALL_MASK, + XILINX_CPM_PCIE_REG_IMR); + + /* Clear pending interrupts */ + pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_IDR) & + XILINX_CPM_PCIE_IMR_ALL_MASK, + XILINX_CPM_PCIE_REG_IDR); + + /* + * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to + * CPM SLCR block. + */ + writel(variant->ir_misc_value, + port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); + + if (variant->ir_enable) { + writel(XILINX_CPM_PCIE_IR_LOCAL, + port->cpm_base + variant->ir_enable); + } - if (variant->ir_enable) { - writel(XILINX_CPM_PCIE_IR_LOCAL, - port->cpm_base + variant->ir_enable); + /* Set Bridge enable bit */ + pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) | + XILINX_CPM_PCIE_REG_RPSC_BEN, + XILINX_CPM_PCIE_REG_RPSC); } - - /* Set Bridge enable bit */ - pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) | - XILINX_CPM_PCIE_REG_RPSC_BEN, - XILINX_CPM_PCIE_REG_RPSC); } /** @@ -578,16 +581,18 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) port->dev = dev; - err = xilinx_cpm_pcie_init_irq_domain(port); - if (err) - return err; + port->variant = of_device_get_match_data(dev); + + if (port->variant->version != CPM5NC_HOST) { + err = xilinx_cpm_pcie_init_irq_domain(port); + if (err) + return err; + } bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); if (!bus) return -ENODEV; - port->variant = of_device_get_match_data(dev); - err = xilinx_cpm_pcie_parse_dt(port, bus->res); if (err) { dev_err(dev, "Parsing DT failed\n"); @@ -596,10 +601,12 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) xilinx_cpm_pcie_init_port(port); - err = xilinx_cpm_setup_irq(port); - if (err) { - dev_err(dev, "Failed to set up interrupts\n"); - goto err_setup_irq; + if (port->variant->version != CPM5NC_HOST) { + err = xilinx_cpm_setup_irq(port); + if (err) { + dev_err(dev, "Failed to set up interrupts\n"); + goto err_setup_irq; + } } bridge->sysdata = port->cfg; @@ -612,11 +619,13 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) return 0; err_host_bridge: - xilinx_cpm_free_interrupts(port); + if (port->variant->version != CPM5NC_HOST) + xilinx_cpm_free_interrupts(port); err_setup_irq: pci_ecam_free(port->cfg); err_parse_dt: - xilinx_cpm_free_irq_domains(port); + if (port->variant->version != CPM5NC_HOST) + xilinx_cpm_free_irq_domains(port); return err; } @@ -639,6 +648,10 @@ static const struct xilinx_cpm_variant cpm5_host1 = { .ir_enable = XILINX_CPM_PCIE1_IR_ENABLE, }; +static const struct xilinx_cpm_variant cpm5n_host = { + .version = CPM5NC_HOST, +}; + static const struct of_device_id xilinx_cpm_pcie_of_match[] = { { .compatible = "xlnx,versal-cpm-host-1.00", @@ -652,6 +665,10 @@ static const struct of_device_id xilinx_cpm_pcie_of_match[] = { .compatible = "xlnx,versal-cpm5-host1", .data = &cpm5_host1, }, + { + .compatible = "xlnx,versal-cpm5nc-host", + .data = &cpm5n_host, + }, {} };