| Message ID | 20250211192444.2292833-3-terry.bowman@amd.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | Enable CXL PCIe port protocol error handling and logging | expand |
On Tue, Feb 11, 2025 at 01:24:29PM -0600, Terry Bowman wrote: > The AER service driver already includes support for Restricted CXL host > (RCH) Downstream Port Protocol Error handling. The current implementation > is based on CXL1.1 using a Root Complex Event Collector. > > Rename function interfaces and parameters where necessary to include > virtual hierarchy (VH) mode CXL PCIe Port error handling alongside the RCH > handling.[1] The CXL PCIe Port Protocol Error handling support will be > added in a future patch. > > Limit changes to renaming variable and function names. No functional > changes are added. > > [1] CXL 3.1 Spec, 9.12.2 CXL Virtual Hierarchy > > Signed-off-by: Terry Bowman <terry.bowman@amd.com> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Reviewed-by: Dave Jiang <dave.jiang@intel.com> > Reviewed-by: Fan Ni <fan.ni@samsung.com> > Reviewed-by: Ira Weiny <ira.weiny@intel.com> > Reviewed-by: Gregory Price <gourry@gourry.net> Acked-by: Bjorn Helgaas <bhelgaas@google.com> > --- > drivers/pci/pcie/aer.c | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) > > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index 508474e17183..6e8de77d0fc4 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -1024,7 +1024,7 @@ static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) > return 0; > } > > -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) > +static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) > { > /* > * Internal errors of an RCEC indicate an AER error in an > @@ -1047,30 +1047,30 @@ static int handles_cxl_error_iter(struct pci_dev *dev, void *data) > return *handles_cxl; > } > > -static bool handles_cxl_errors(struct pci_dev *rcec) > +static bool handles_cxl_errors(struct pci_dev *dev) > { > bool handles_cxl = false; > > - if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC && > - pcie_aer_is_native(rcec)) > - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); > + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && > + pcie_aer_is_native(dev)) > + pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); > > return handles_cxl; > } > > -static void cxl_rch_enable_rcec(struct pci_dev *rcec) > +static void cxl_enable_internal_errors(struct pci_dev *dev) > { > - if (!handles_cxl_errors(rcec)) > + if (!handles_cxl_errors(dev)) > return; > > - pci_aer_unmask_internal_errors(rcec); > - pci_info(rcec, "CXL: Internal errors unmasked"); > + pci_aer_unmask_internal_errors(dev); > + pci_info(dev, "CXL: Internal errors unmasked"); > } > > #else > -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } > -static inline void cxl_rch_handle_error(struct pci_dev *dev, > - struct aer_err_info *info) { } > +static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } > +static inline void cxl_handle_error(struct pci_dev *dev, > + struct aer_err_info *info) { } > #endif > > /** > @@ -1108,7 +1108,7 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) > > static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) > { > - cxl_rch_handle_error(dev, info); > + cxl_handle_error(dev, info); > pci_aer_handle_error(dev, info); > pci_dev_put(dev); > } > @@ -1491,7 +1491,7 @@ static int aer_probe(struct pcie_device *dev) > return status; > } > > - cxl_rch_enable_rcec(port); > + cxl_enable_internal_errors(port); > aer_enable_rootport(rpc); > pci_info(port, "enabled with IRQ %d\n", dev->irq); > return 0; > -- > 2.34.1 >
Terry Bowman wrote: > The AER service driver already includes support for Restricted CXL host > (RCH) Downstream Port Protocol Error handling. The current implementation > is based on CXL1.1 using a Root Complex Event Collector. > > Rename function interfaces and parameters where necessary to include > virtual hierarchy (VH) mode CXL PCIe Port error handling alongside the RCH > handling.[1] The CXL PCIe Port Protocol Error handling support will be > added in a future patch. > > Limit changes to renaming variable and function names. No functional > changes are added. > > [1] CXL 3.1 Spec, 9.12.2 CXL Virtual Hierarchy > > Signed-off-by: Terry Bowman <terry.bowman@amd.com> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Reviewed-by: Dave Jiang <dave.jiang@intel.com> > Reviewed-by: Fan Ni <fan.ni@samsung.com> > Reviewed-by: Ira Weiny <ira.weiny@intel.com> > Reviewed-by: Gregory Price <gourry@gourry.net> Looks good: Reviewed-by: Dan Williams <dan.j.williams@intel.com>
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 508474e17183..6e8de77d0fc4 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1024,7 +1024,7 @@ static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) return 0; } -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) +static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) { /* * Internal errors of an RCEC indicate an AER error in an @@ -1047,30 +1047,30 @@ static int handles_cxl_error_iter(struct pci_dev *dev, void *data) return *handles_cxl; } -static bool handles_cxl_errors(struct pci_dev *rcec) +static bool handles_cxl_errors(struct pci_dev *dev) { bool handles_cxl = false; - if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && + pcie_aer_is_native(dev)) + pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); return handles_cxl; } -static void cxl_rch_enable_rcec(struct pci_dev *rcec) +static void cxl_enable_internal_errors(struct pci_dev *dev) { - if (!handles_cxl_errors(rcec)) + if (!handles_cxl_errors(dev)) return; - pci_aer_unmask_internal_errors(rcec); - pci_info(rcec, "CXL: Internal errors unmasked"); + pci_aer_unmask_internal_errors(dev); + pci_info(dev, "CXL: Internal errors unmasked"); } #else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } -static inline void cxl_rch_handle_error(struct pci_dev *dev, - struct aer_err_info *info) { } +static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } +static inline void cxl_handle_error(struct pci_dev *dev, + struct aer_err_info *info) { } #endif /** @@ -1108,7 +1108,7 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) { - cxl_rch_handle_error(dev, info); + cxl_handle_error(dev, info); pci_aer_handle_error(dev, info); pci_dev_put(dev); } @@ -1491,7 +1491,7 @@ static int aer_probe(struct pcie_device *dev) return status; } - cxl_rch_enable_rcec(port); + cxl_enable_internal_errors(port); aer_enable_rootport(rpc); pci_info(port, "enabled with IRQ %d\n", dev->irq); return 0;