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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5462006b0ecsm559806e87.160.2025.02.17.10.56.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2025 10:56:28 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 17 Feb 2025 20:56:17 +0200 Subject: [PATCH 5/6] arm64: dts: qcom: sar2130p: add PCIe EP device nodes Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250217-sar2130p-pci-v1-5-94b20ec70a14@linaro.org> References: <20250217-sar2130p-pci-v1-0-94b20ec70a14@linaro.org> In-Reply-To: <20250217-sar2130p-pci-v1-0-94b20ec70a14@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2579; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=0x/IfIzQT4GRcmYt63ztDRrOia/9PgQl3I9hd35sLvo=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBns4ZRXOd9ZqtUphIXC4hj+NDEExWJk57dly67s WwCzIKxQISJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7OGUQAKCRAU23LtvoBl uKfjEACvUBBHL0bgMi6vB2fzerFZ4siCzVDda/rqN+4TVy+rQjSQg5uDKRE6bh1IUnMcrdaoKTa zKQr4mG4Fm7LrgE7qpSzbhlOT/klwvSksaiZ54EAcRIQSCga27OFcSBhL29Z79JM3OK0WVEyW0S 3sHjS6fNmVuTPJozCkkDHUJxekWEasBDiQ+uiAdszvHgr/FpQxM64yCqAwUPuJJdtMom/H2nGZ9 I2JnNKxN4Gt7x4rkAXVEkxWqHwgLTNa49k3d7uiTCDwxNhQNMZVUtZw0gKjuVtLH0b2FOZWJyFx aXs13tHp2kQ+UK2DI33L7bDy6D0GomI37ix93DRji/MVDxgsetKuuDQOhH1f09Bq8FlTa7XGZAm jdpKnho0SqkjoQQq7q3j3eZ6zjQopoXpkrCxt59937K9lzmijfIytB0lvnmaSjorsoSJ8V5ZjYh yCa/SEsof+zY0qpsyNwg+VJSS97SuKoVtwuGuHXAoQXvwSCg7osKZDZfv/7DvFto/vvZpQajijH ww+gx3Jh/0x6yh7+IkcAlJS5Cm3iMHYILGudJnSQDHeKkcJB6U7wXicr9rTfGmJa4jdkv2pD8d9 IcXmiYDxC1DNQDQ5dedVQropnZcxuYdWLaqizy5eMzrj6RbcFLjYzHWxCPdLduIzWCL90ZcPN5i y5LRF21DHZ+lmVw== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On the Qualcomm AR2 Gen1 platform the second PCIe host can be used either as an RC or as an EP device. Add device node for the PCIe EP. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 53 ++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index dd832e6816be85817fd1ecc853f8d4c800826bc4..7f007fad6eceebac1b2a863d9f85f2ce3dfb926a 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1474,6 +1474,59 @@ pcie@0 { }; }; + pcie1_ep: pcie-ep@1c08000 { + compatible = "qcom,sar2130p-pcie-ep"; + reg = <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40200000 0x0 0x1000000>, + <0x0 0x01c0b000 0x0 0x1000>, + <0x0 0x40002000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, + <&gcc GCC_QMIP_PCIE_AHB_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre_noc_axi", + "cnoc_sf_axi", + "qmip_pcie_ahb"; + + interrupts = , + , + ; + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", "cpu-pcie"; + iommus = <&apps_smmu 0x1e00 0x1>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + num-lanes = <2>; + + status = "disabled"; + }; + pcie1_phy: phy@1c0e000 { compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy"; reg = <0x0 0x01c0e000 0x0 0x2000>;