| Message ID | 20250217-sar2130p-pci-v1-6-94b20ec70a14@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | PCI: qcom-ep: add support for using the EP on SAR2130P and SM8450 | expand |
On 17.02.2025 7:56 PM, Dmitry Baryshkov wrote: > On the Qualcomm SM8450 platform the second PCIe host can be used > either as an RC or as an EP device. Add device node for the PCIe EP. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 52 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 52 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 9c809fc5fa45a98ff5441a0b6809931588897243..ad0ec15b18e5ca7bea196be1564152f7faf51d9f 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -2262,6 +2262,58 @@ pcie@0 { > }; > }; > > + pcie1_ep: pcie-ep@1c08000 { > + compatible = "qcom,sm8450-pcie-ep"; > + reg = <0x0 0x01c08000 0x0 0x3000>, > + <0x0 0x40000000 0x0 0xf1d>, > + <0x0 0x40000f20 0x0 0xa8>, > + <0x0 0x40001000 0x0 0x1000>, > + <0x0 0x40200000 0x0 0x1000000>, > + <0x0 0x01c0b000 0x0 0x1000>, > + <0x0 0x40002000 0x0 0x1000>; > + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", > + "mmio", "dma"; > + > + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, > + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a", > + "ref", > + "ddrss_sf_tbu", > + "aggre_noc_axi"; > + > + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "global", "doorbell", "dma"; > + > + interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; same comments as patch 5, plus please use tags Konrad
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9c809fc5fa45a98ff5441a0b6809931588897243..ad0ec15b18e5ca7bea196be1564152f7faf51d9f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2262,6 +2262,58 @@ pcie@0 { }; }; + pcie1_ep: pcie-ep@1c08000 { + compatible = "qcom,sm8450-pcie-ep"; + reg = <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40200000 0x0 0x1000000>, + <0x0 0x01c0b000 0x0 0x1000>, + <0x0 0x40002000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "ddrss_sf_tbu", + "aggre_noc_axi"; + + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommus = <&apps_smmu 0x1c80 0x7f>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + num-lanes = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "disabled"; + }; + pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; reg = <0 0x01c0e000 0 0x2000>;
On the Qualcomm SM8450 platform the second PCIe host can be used either as an RC or as an EP device. Add device node for the PCIe EP. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 52 ++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+)