From patchwork Thu Sep 22 20:20:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 9346877 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A33BE60757 for ; Thu, 22 Sep 2016 20:20:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 946932AC8D for ; Thu, 22 Sep 2016 20:20:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 88A532ACED; Thu, 22 Sep 2016 20:20:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 06C3A2ACD6 for ; Thu, 22 Sep 2016 20:20:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935171AbcIVUUZ (ORCPT ); Thu, 22 Sep 2016 16:20:25 -0400 Received: from mail-lf0-f45.google.com ([209.85.215.45]:34674 "EHLO mail-lf0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937881AbcIVUUY (ORCPT ); Thu, 22 Sep 2016 16:20:24 -0400 Received: by mail-lf0-f45.google.com with SMTP id y6so78087772lff.1 for ; Thu, 22 Sep 2016 13:20:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:organization:user-agent :mime-version:content-transfer-encoding; bh=MG4hOgHHT6zHj+ftnFPyNfbMroCT6jYwYXUj4JwzBK4=; b=HAr0W6nMV4RLdOns7SE45NRS34sPk9TL7f+ANLkkscRKZn8FTrDFyNAG9eG2nKb1QY p6u8sDuvZ5cJO6wM4TfmHlkSxE0tpnmYEusBUjdArNPaaqqUYh3k7tx6P0E2+ZtTdE1C f7uZzagFt5+0Xk1PUboXHZQ/oXaPQIgy63DhbkkgFQkXzBOJtJ8H3RTs/fNJyTh2aky4 CW0e8w6pRuxfTdelZuSmuVrwfwZkU12HeygufHjy5w7YgkqhEmAVmu0fD0/FXU94M9FD lkzm0it22uYZ5R8mmPm7rca61pmybebImLsZ0/NshaHA1SAy2DjHoc8NzrenEeZEeFT+ ZE5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:organization :user-agent:mime-version:content-transfer-encoding; bh=MG4hOgHHT6zHj+ftnFPyNfbMroCT6jYwYXUj4JwzBK4=; b=jDpMDfb+k2iVBk7PgKsy5bLVm8jbT6gJhM1tYvyfyWGn0lpDtnKRD/QpuqeJm1LGOc fzYiiAWp2E8iLslLLaa5RbpnupQJFxL6mm3E6RZkWheCZNIZK/PnejR/pJ58r7nOwYk9 gUiSo4fxwrcREikM5xzpgbNHlAkjnFcCXUbmI67s9Qo+Ml9Sc9IVXexRUjtyNfoisIWi ixiEH2Jcgb7fnRqTW2167vr7mnOpDznvYzTo86nHS2rhDJqN0JkAqckgWawcF5T3dF/F PGslmHnXjc6a9SfbTE1IoKT0M94/cRpFBQ7Fch3eC3Lqa8LdHYdfpGxrXr4p84Pg6g47 ppoA== X-Gm-Message-State: AE9vXwNJ+EzoNjbiuotSzcYKyEx1nIrpS8lPl7Cm71X9HrQ5ku8cIJL6BKG66sOPBeQQgg== X-Received: by 10.46.32.5 with SMTP id g5mr1548116ljg.51.1474575620647; Thu, 22 Sep 2016 13:20:20 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.84.137]) by smtp.gmail.com with ESMTPSA id g38sm607284ljg.24.2016.09.22.13.20.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Sep 2016 13:20:19 -0700 (PDT) From: Sergei Shtylyov To: horms@verge.net.au, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2] pcie-rcar: try setting PCIe speed to 5 GT/s at boot Date: Thu, 22 Sep 2016 23:20:18 +0300 Message-ID: <3386780.3qrqUfW7i7@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.10 (Linux/4.7.3-100.fc23.x86_64; KDE/4.14.20; x86_64; ; ) MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Initially, the PCIe link speed is set up only at 2.5 GT/s. For better performance, we're trying to increase link speed to 5 GT/s. Based on the original patch by Grigory Kletsko . Signed-off-by: Sergei Shtylyov Acked-by: Simon Horman --- The patch is against the 'next' branch of Bjorn Helgaas' 'pci.git' repo. Changes in version 2: - switched from the interrupt based speed change algorithm to polling with 1-second timeout, got rid of the now unneeded register/bit #define's; - made rcar_pcie_force_speedup() *static*; - moved the speed capability check to the start of rcar_pcie_force_speedup(); - adjusted the speed change in-progress check and the error message; - read MACSR ony once during the speed change setup; - print current link speed after any speed change outcome and when the speed is already 5 GT/s; - removed the TODO comment; - moved rcar_pcie_force_speedup() call to the start of rcar_pcie_enable(); - changed the patch authorship, updated the patch description accordingly. drivers/pci/host/pcie-rcar.c | 70 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: pci/drivers/pci/host/pcie-rcar.c =================================================================== --- pci.orig/drivers/pci/host/pcie-rcar.c +++ pci/drivers/pci/host/pcie-rcar.c @@ -84,8 +84,19 @@ #define IDSETR1 0x011004 #define TLCTLR 0x011048 #define MACSR 0x011054 +#define SPCHG (1 << 5) +#define SPCHGFIN (1 << 4) +#define SPCHGSUC (1 << 7) +#define SPCHGFAIL (1 << 6) +#define LINK_SPEED (0xf << 16) +#define LINK_SPEED_2_5GTS (1 << 16) +#define LINK_SPEED_5_0GTS (2 << 16) #define MACCTLR 0x011058 +#define SPEED_CHANGE (1 << 24) #define SCRAMBLE_DISABLE (1 << 27) +#define MACS2R 0x011078 +#define MACCGSPSETR 0x011084 +#define SPCNGRSN (1 << 31) /* R-Car H1 PHY */ #define H1_PCIEPHYADRR 0x04000c @@ -385,11 +396,70 @@ static int rcar_pcie_setup(struct list_h return 1; } +static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) +{ + unsigned int timeout = 1000; + u32 macsr; + + if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) + return; + + dev_info(pcie->dev, "Trying speed up to 5 GT/s\n"); + + if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { + dev_err(pcie->dev, "Speed change is in progress\n"); + return; + } + + macsr = rcar_pci_read_reg(pcie, MACSR); + if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) + goto done; + + /* Set target link speed to 5.0 GT/s */ + rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, + PCI_EXP_LNKSTA_CLS_5_0GB); + + /* Set speed change reason as intentional factor */ + rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); + + /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ + if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) + rcar_pci_write_reg(pcie, macsr, MACSR); + + /* Start link speed change */ + rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); + + while (timeout--) { + macsr = rcar_pci_read_reg(pcie, MACSR); + if (macsr & SPCHGFIN) { + /* Clear the interrupt bits */ + rcar_pci_write_reg(pcie, macsr, MACSR); + + if (macsr & SPCHGFAIL) + dev_err(pcie->dev, "Speed change failed\n"); + + goto done; + } + + msleep(1); + }; + + dev_err(pcie->dev, "Speed change timed out\n"); + +done: + /* Check speed */ + dev_info(pcie->dev, "Current link speed is %s GT/s\n", + (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); +} + static int rcar_pcie_enable(struct rcar_pcie *pcie) { struct pci_bus *bus, *child; LIST_HEAD(res); + /* Try setting 5 GT/s link speed */ + rcar_pcie_force_speedup(pcie); + rcar_pcie_setup(&res, pcie); pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);