From patchwork Sun Apr 8 18:05:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10328463 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 51F0C604D4 for ; Sun, 8 Apr 2018 18:05:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3DC9428943 for ; Sun, 8 Apr 2018 18:05:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2E3B4289F2; Sun, 8 Apr 2018 18:05:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 93E5C28943 for ; Sun, 8 Apr 2018 18:05:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752238AbeDHSFP (ORCPT ); Sun, 8 Apr 2018 14:05:15 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:54489 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751702AbeDHSFO (ORCPT ); Sun, 8 Apr 2018 14:05:14 -0400 Received: by mail-wm0-f68.google.com with SMTP id r191so13355342wmg.4 for ; Sun, 08 Apr 2018 11:05:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=subject:from:to:references:cc:organization:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=UDj+tAC8bfsWBqyGtU6oYpv/DvpXzPW1vmovMMt8DEY=; b=r1v4A4uXZYUN182dygiJTSxcIoaB8XkYsau4feDCN/XHXIFLy6EkOBL9MV0x+mRHRp L7PUWaStsksnfbDF0DkTR+LLdxOWEgIy1bZEQa0LIHv8eN4kfpficzOrUXYbQr8FhUtQ WKIVfbvFxRSi1FPQzEEKs/MvHL7DxYedVpZu6RFNh9D/IdxpfpyoY0QSt5mmnLfq9fD6 H2Ioh34rnAZPnoDp6AQiJ0RvUMy3mWJPvvEOIuaD3F06Fj5MwPXkkfgM23wBga0RwFLr cUVxdVmpcK5IP0+c2VYqqnGEbPmMyokAY+0l0CyIZW9ARcMw8tS0OppguGOxDnu06Tsg 4/gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:references:cc:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=UDj+tAC8bfsWBqyGtU6oYpv/DvpXzPW1vmovMMt8DEY=; b=ddmxKrp7e1WXmOt0PZ4mo6T4YbuJ9zkLCfwBKJgav2b3VG6lbJ2951/BHiiUwdQIIo LVupL9D+pLVO3gumWhY2RR6oX5hiNmK09jnRfMTUhUcuXTQBuH3lLI2aLSeadYJi9IME j+L4+/HBo0YQso/+LtyesmI/6zuvMGYfMw31DOhbf+qn6GYNVhR66bNTlXO4GlErkcrf C+E14MXupZRp7e3R5O3PPUnJgJ6NXVkt+XwJfxjwaaQSYcNIoWOY18NC4GACsAlL4Vom nPxZ41fMhdnxzku8cFlcUznxAFmOVe37LGj/xRboZuuGVlFdCJj/XLsM2skABWvg5Rn5 FgQA== X-Gm-Message-State: AElRT7FnCgs56rpaIPQv0SOzSkUiG70INa4ZLXoqGhBs8wkrbxW8YWGT 4zu4jN1fN9M7wwdHybH/jDzNyQ== X-Google-Smtp-Source: AIpwx4/93PSXnjMkp489eeBiJThmLQiMS0KyT9sgGfnQ9uOorLx1nBB/Uz2xqHdxj94/JIwLa7E6DA== X-Received: by 10.46.32.154 with SMTP id g26mr20970046lji.71.1523210712631; Sun, 08 Apr 2018 11:05:12 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.81.34]) by smtp.gmail.com with ESMTPSA id x62-v6sm3037733lfd.82.2018.04.08.11.05.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 08 Apr 2018 11:05:11 -0700 (PDT) Subject: [PATCH v2 3/5] pcie-rcar: add R-Car gen3 PHY support From: Sergei Shtylyov To: horms@verge.net.au, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Lorenzo Pieralisi , Rob Herring , "devicetree@vger.kernel.org" References: <26e803ca-06b6-28c5-b87c-fc639b322d6f@cogentembedded.com> Cc: Mark Rutland Organization: Cogent Embedded Message-ID: <3eb7e548-8b21-2347-c742-a007fd9cfed9@cogentembedded.com> Date: Sun, 8 Apr 2018 21:05:10 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <26e803ca-06b6-28c5-b87c-fc639b322d6f@cogentembedded.com> Content-Language: en-MW Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On R-Car gen3 SoCs the PCIe PHY has its own register region -- and I have written a generic PHY driver for it, thus we need to add the corresponding code in rcar_pcie_hw_init_gen3() and call devm_phy_optional_get() at the driver's probing time, so that the existing R-Car gen3 device trees (not having a PHY node) would still work (we only need to power up the PHY on R-Car V3H). Signed-off-by: Sergei Shtylyov Reviewed-by: Rob Herring --- Changes in version 2: - updated the bindings. Documentation/devicetree/bindings/pci/rcar-pci.txt | 5 +++ drivers/pci/host/pcie-rcar.c | 27 +++++++++++++++++++-- 2 files changed, 30 insertions(+), 2 deletions(-) Index: pci/Documentation/devicetree/bindings/pci/rcar-pci.txt =================================================================== --- pci.orig/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ pci/Documentation/devicetree/bindings/pci/rcar-pci.txt @@ -32,6 +32,11 @@ compatible: "renesas,pcie-r8a7743" for t and PCIe bus clocks. - clock-names: from common clock binding: should be "pcie" and "pcie_bus". +Optional properties: +- phys: from common PHY binding: PHY phandle and specifier (only make sense + for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks). +- phy-names: from common PHY binding: should be "pcie". + Example: SoC-specific DT Entry: Index: pci/drivers/pci/host/pcie-rcar.c =================================================================== --- pci.orig/drivers/pci/host/pcie-rcar.c +++ pci/drivers/pci/host/pcie-rcar.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -140,6 +141,7 @@ static inline struct rcar_msi *to_rcar_m /* Structure representing the PCIe interface */ struct rcar_pcie { struct device *dev; + struct phy *phy; void __iomem *base; struct list_head resources; int root_bus_nr; @@ -667,6 +669,21 @@ static int rcar_pcie_hw_init_gen2(struct return rcar_pcie_hw_init(pcie); } +static int rcar_pcie_hw_init_gen3(struct rcar_pcie *pcie) +{ + int err; + + err = phy_init(pcie->phy); + if (err) + return err; + + err = phy_power_on(pcie->phy); + if (err) + return err; + + return rcar_pcie_hw_init(pcie); +} + static int rcar_msi_alloc(struct rcar_msi *chip) { int msi; @@ -916,6 +933,10 @@ static int rcar_pcie_get_resources(struc struct resource res; int err, i; + pcie->phy = devm_phy_optional_get(dev, "pcie"); + if (IS_ERR(pcie->phy)) + return PTR_ERR(pcie->phy); + err = of_address_to_resource(dev->of_node, 0, &res); if (err) return err; @@ -1068,8 +1089,10 @@ static const struct of_device_id rcar_pc .data = rcar_pcie_hw_init_gen2 }, { .compatible = "renesas,pcie-rcar-gen2", .data = rcar_pcie_hw_init_gen2 }, - { .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init }, - { .compatible = "renesas,pcie-rcar-gen3", .data = rcar_pcie_hw_init }, + { .compatible = "renesas,pcie-r8a7795", + .data = rcar_pcie_hw_init_gen3 }, + { .compatible = "renesas,pcie-rcar-gen3", + .data = rcar_pcie_hw_init_gen3 }, {}, };