From patchwork Wed May 13 05:06:30 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hidetoshi Seto X-Patchwork-Id: 23492 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n4D57TH4027466 for ; Wed, 13 May 2009 05:07:29 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750893AbZEMFHY (ORCPT ); Wed, 13 May 2009 01:07:24 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751422AbZEMFHY (ORCPT ); Wed, 13 May 2009 01:07:24 -0400 Received: from fgwmail7.fujitsu.co.jp ([192.51.44.37]:53998 "EHLO fgwmail7.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750893AbZEMFHW (ORCPT ); Wed, 13 May 2009 01:07:22 -0400 Received: from m2.gw.fujitsu.co.jp ([10.0.50.72]) by fgwmail7.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id n4D57Mc4021263 (envelope-from seto.hidetoshi@jp.fujitsu.com); Wed, 13 May 2009 14:07:23 +0900 Received: from smail (m2 [127.0.0.1]) by outgoing.m2.gw.fujitsu.co.jp (Postfix) with ESMTP id ABC0D45DE57; Wed, 13 May 2009 14:07:22 +0900 (JST) Received: from s2.gw.fujitsu.co.jp (s2.gw.fujitsu.co.jp [10.0.50.92]) by m2.gw.fujitsu.co.jp (Postfix) with ESMTP id 8B25045DD79; Wed, 13 May 2009 14:07:22 +0900 (JST) Received: from s2.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s2.gw.fujitsu.co.jp (Postfix) with ESMTP id 6CC991DB803C; Wed, 13 May 2009 14:07:22 +0900 (JST) Received: from ml14.s.css.fujitsu.com (ml14.s.css.fujitsu.com [10.249.87.104]) by s2.gw.fujitsu.co.jp (Postfix) with ESMTP id 254441DB8038; Wed, 13 May 2009 14:07:22 +0900 (JST) Received: from ml14.css.fujitsu.com (ml14 [127.0.0.1]) by ml14.s.css.fujitsu.com (Postfix) with ESMTP id C7DFC9F60BE; Wed, 13 May 2009 14:07:21 +0900 (JST) Received: from [127.0.0.1] (unknown [10.124.100.141]) by ml14.s.css.fujitsu.com (Postfix) with ESMTP id 4C2999F60B4; Wed, 13 May 2009 14:07:21 +0900 (JST) Message-ID: <4A0A5556.9050209@jp.fujitsu.com> Date: Wed, 13 May 2009 14:06:30 +0900 From: Hidetoshi Seto User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 To: Matthew Wilcox CC: Jesse Barnes , "David S. Miller" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] PCI MSI: Yet another fix for MSI-X with NIU cards, v2 References: <20090508131333.GV8112@parisc-linux.org> <4A0A5284.1000705@jp.fujitsu.com> In-Reply-To: <4A0A5284.1000705@jp.fujitsu.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi David and all, Sorry, if you have problem with wrong diffstat in patch header (it was because I hand-fixed the comment in patch), please use following instead. Contents are not changed, still v2. Thanks, H.Seto The NIU device refuses to allow accesses to MSI-X registers before MSI-X is enabled. This patch fixes the problem by moving the read & write the mask register (for preserved bits) to after MSI-X is enabled. Reported-by: David S. Miller Signed-off-by: Hidetoshi Seto Acked-by: Michael Ellerman --- drivers/pci/msi.c | 21 ++++++++++++++++++--- 1 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 6f2e629..44085e0 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -455,9 +455,7 @@ static int msix_capability_init(struct pci_dev *dev, entry->msi_attrib.default_irq = dev->irq; entry->msi_attrib.pos = pos; entry->mask_base = base; - entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE + - PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); - msix_mask_irq(entry, 1); + entry->masked = 1; list_add_tail(&entry->list, &dev->msi_list); } @@ -493,6 +491,23 @@ static int msix_capability_init(struct pci_dev *dev, msix_set_enable(dev, 1); dev->msix_enabled = 1; + /* + * The states of Reserved bits[31:01] of Vector Control for MSI-X + * Table Entries must be 0. However, for potential future use, + * software must preserve the value of these reserved bits. + * Refer PCI spec 3.0, 6.8.2.9. + * + * Note that there are some device that refuses access to MSI-X + * Table Entries before MSI-X is enabled. Therefore we do it here. + */ + list_for_each_entry(entry, &dev->msi_list, list) { + int vector = entry->msi_attrib.entry_nr; + entry->masked = readl(base + vector * PCI_MSIX_ENTRY_SIZE + + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); + /* Make sure it is masked */ + msix_mask_irq(entry, 1); + } + return 0; }