===================================================================
@@ -186,6 +186,7 @@ static void pcie_aspm_configure_common_c
unsigned long start_jiffies;
struct pci_dev *child, *parent = link->pdev;
struct pci_bus *linkbus = parent->subordinate;
+ bool ccc_updated = false;
/*
* All functions of a slot should have the same Slot Clock
* Configuration, so just check one function
@@ -214,7 +215,10 @@ static void pcie_aspm_configure_common_c
reg16 |= PCI_EXP_LNKCTL_CCC;
else
reg16 &= ~PCI_EXP_LNKCTL_CCC;
+ if (reg16 == child_reg[PCI_FUNC(child->devfn)])
+ continue;
pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16);
+ ccc_updated = true;
}
/* Configure upstream component */
@@ -224,7 +228,14 @@ static void pcie_aspm_configure_common_c
reg16 |= PCI_EXP_LNKCTL_CCC;
else
reg16 &= ~PCI_EXP_LNKCTL_CCC;
- pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
+ if (reg16 != parent_reg) {
+ pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
+ ccc_updated = true;
+ }
+
+ /* Don't need to retrain link if there is no change in CCC */
+ if (!ccc_updated)
+ return;
/* Retrain link */
reg16 |= PCI_EXP_LNKCTL_RL;