From patchwork Wed Nov 25 12:06:51 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kenji Kaneshige X-Patchwork-Id: 62765 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id nAPC6aIM016595 for ; Wed, 25 Nov 2009 12:07:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758753AbZKYMHG (ORCPT ); Wed, 25 Nov 2009 07:07:06 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1758758AbZKYMHG (ORCPT ); Wed, 25 Nov 2009 07:07:06 -0500 Received: from fgwmail5.fujitsu.co.jp ([192.51.44.35]:54826 "EHLO fgwmail5.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758753AbZKYMHF (ORCPT ); Wed, 25 Nov 2009 07:07:05 -0500 Received: from m6.gw.fujitsu.co.jp ([10.0.50.76]) by fgwmail5.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id nAPC7Aac032175 for (envelope-from kaneshige.kenji@jp.fujitsu.com); Wed, 25 Nov 2009 21:07:11 +0900 Received: from smail (m6 [127.0.0.1]) by outgoing.m6.gw.fujitsu.co.jp (Postfix) with ESMTP id 5E9C045DE52 for ; Wed, 25 Nov 2009 21:07:10 +0900 (JST) Received: from s6.gw.fujitsu.co.jp (s6.gw.fujitsu.co.jp [10.0.50.96]) by m6.gw.fujitsu.co.jp (Postfix) with ESMTP id 110D445DE4F for ; Wed, 25 Nov 2009 21:07:10 +0900 (JST) Received: from s6.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s6.gw.fujitsu.co.jp (Postfix) with ESMTP id DF67D1DB803F for ; Wed, 25 Nov 2009 21:07:09 +0900 (JST) Received: from m108.s.css.fujitsu.com (m108.s.css.fujitsu.com [10.249.87.108]) by s6.gw.fujitsu.co.jp (Postfix) with ESMTP id 84B051DB8037 for ; Wed, 25 Nov 2009 21:07:09 +0900 (JST) Received: from m108.css.fujitsu.com (m108 [127.0.0.1]) by m108.s.css.fujitsu.com (Postfix) with ESMTP id 5B26F428057; Wed, 25 Nov 2009 21:07:09 +0900 (JST) Received: from [127.0.0.1] (unknown [10.124.100.137]) by m108.s.css.fujitsu.com (Postfix) with ESMTP id 07706428054; Wed, 25 Nov 2009 21:07:09 +0900 (JST) X-SecurityPolicyCheck-FJ: OK by FujitsuOutboundMailChecker v1.3.1 Received: from KANE-LIFEBOOK[10.124.100.137] by KANE-LIFEBOOK (FujitsuOutboundMailChecker v1.3.1/9992[10.124.100.137]); Wed, 25 Nov 2009 21:06:55 +0900 (JST) Message-ID: <4B0D1DDB.8080405@jp.fujitsu.com> Date: Wed, 25 Nov 2009 21:06:51 +0900 From: Kenji Kaneshige User-Agent: Thunderbird 2.0.0.23 (Windows/20090812) MIME-Version: 1.0 To: linux-pci@vger.kernel.org, jbarnes@virtuousgeek.org Subject: [PATCH 11/11] portdrv: remove redundant definitions References: <4B0D1C19.8060201@jp.fujitsu.com> In-Reply-To: <4B0D1C19.8060201@jp.fujitsu.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Index: 20091125/drivers/pci/pcie/portdrv.h =================================================================== --- 20091125.orig/drivers/pci/pcie/portdrv.h +++ 20091125/drivers/pci/pcie/portdrv.h @@ -11,24 +11,10 @@ #include -#if !defined(PCI_CAP_ID_PME) -#define PCI_CAP_ID_PME 1 -#endif - -#if !defined(PCI_CAP_ID_EXP) -#define PCI_CAP_ID_EXP 0x10 -#endif - -#define PORT_TYPE_MASK 0xf -#define PORT_TO_SLOT_MASK 0x100 -#define SLOT_HP_CAPABLE_MASK 0x40 -#define PCIE_CAPABILITIES_REG 0x2 -#define PCIE_SLOT_CAPABILITIES_REG 0x14 -#define PCIE_PORT_DEVICE_MAXSERVICES 4 -#define PCIE_PORT_MSI_VECTOR_MASK 0x1f +#define PCIE_PORT_DEVICE_MAXSERVICES 4 /* - * According to the PCI Express Base Specification 2.0, the indices of the MSI-X - * table entires used by port services must not exceed 31 + * According to the PCI Express Base Specification 2.0, the indices of + * the MSI-X table entires used by port services must not exceed 31 */ #define PCIE_PORT_MAX_MSIX_ENTRIES 32 Index: 20091125/drivers/pci/pcie/portdrv_core.c =================================================================== --- 20091125.orig/drivers/pci/pcie/portdrv_core.c +++ 20091125/drivers/pci/pcie/portdrv_core.c @@ -109,8 +109,8 @@ static int pcie_port_enable_msix(struct * used to generate the interrupt message." */ pos = pci_pcie_cap(dev); - pci_read_config_word(dev, pos + PCIE_CAPABILITIES_REG, ®16); - entry = (reg16 >> 9) & PCIE_PORT_MSI_VECTOR_MASK; + pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); + entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9; if (entry >= nr_entries) goto Error; @@ -230,12 +230,11 @@ static int get_port_device_capability(st u32 reg32; pos = pci_pcie_cap(dev); - pci_read_config_word(dev, pos + PCIE_CAPABILITIES_REG, ®16); + pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); /* Hot-Plug Capable */ - if (reg16 & PORT_TO_SLOT_MASK) { - pci_read_config_dword(dev, - pos + PCIE_SLOT_CAPABILITIES_REG, ®32); - if (reg32 & SLOT_HP_CAPABLE_MASK) + if (reg16 & PCI_EXP_FLAGS_SLOT) { + pci_read_config_dword(dev, pos + PCI_EXP_SLTCAP, ®32); + if (reg32 & PCI_EXP_SLTCAP_HPC) services |= PCIE_PORT_SERVICE_HP; } /* AER capable */