From patchwork Tue Jul 5 08:01:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naoki Yanagimoto X-Patchwork-Id: 943722 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p6582BvN029177 for ; Tue, 5 Jul 2011 08:02:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754467Ab1GEICJ (ORCPT ); Tue, 5 Jul 2011 04:02:09 -0400 Received: from fgwmail5.fujitsu.co.jp ([192.51.44.35]:42339 "EHLO fgwmail5.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754353Ab1GEICH (ORCPT ); Tue, 5 Jul 2011 04:02:07 -0400 Received: from m1.gw.fujitsu.co.jp (unknown [10.0.50.71]) by fgwmail5.fujitsu.co.jp (Postfix) with ESMTP id 969A03EE0AE for ; Tue, 5 Jul 2011 17:02:05 +0900 (JST) Received: from smail (m1 [127.0.0.1]) by outgoing.m1.gw.fujitsu.co.jp (Postfix) with ESMTP id 7F96445DE54 for ; Tue, 5 Jul 2011 17:02:05 +0900 (JST) Received: from s1.gw.fujitsu.co.jp (s1.gw.fujitsu.co.jp [10.0.50.91]) by m1.gw.fujitsu.co.jp (Postfix) with ESMTP id 5D55245DE55 for ; Tue, 5 Jul 2011 17:02:05 +0900 (JST) Received: from s1.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s1.gw.fujitsu.co.jp (Postfix) with ESMTP id 4ECF91DB804A for ; Tue, 5 Jul 2011 17:02:05 +0900 (JST) Received: from m005.s.css.fujitsu.com (m005.s.css.fujitsu.com [10.23.4.35]) by s1.gw.fujitsu.co.jp (Postfix) with ESMTP id 15F621DB804B for ; Tue, 5 Jul 2011 17:02:05 +0900 (JST) Received: from m005.css.fujitsu.com (m005 [127.0.0.1]) by m005.s.css.fujitsu.com (Postfix) with ESMTP id 6206C50EBD6; Tue, 5 Jul 2011 17:02:04 +0900 (JST) Received: from [127.0.0.1] (unknown [10.124.101.136]) by m005.s.css.fujitsu.com (Postfix) with ESMTP id DAC8350EBD5; Tue, 5 Jul 2011 17:02:03 +0900 (JST) X-SecurityPolicyCheck: OK by SHieldMailChecker v1.5.1 Message-ID: <4E12C4F6.6060301@np.css.fujitsu.com> Date: Tue, 05 Jul 2011 17:01:58 +0900 From: Naoki Yanagimoto User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; ja; rv:1.9.2.18) Gecko/20110616 Thunderbird/3.1.11 MIME-Version: 1.0 To: linux-pci@vger.kernel.org CC: jbarnes@virtuousgeek.org, kaneshige.kenji@jp.fujitsu.com Subject: [patch] PCI: pciehp: Wait for 1 second in board_added() for a Valid Configuration Request Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 05 Jul 2011 08:02:11 +0000 (UTC) From: Naoki Yanagimoto I got a problem that an abnormal value was returned from the configuration space of some PCIe card at hotadd. The pciehp driver regarded the function of the device as being unavailable, so the card did not work. The problem disappeared when I simply added 1 second wait without using DLLLA. I think that it should wait for 1 second because "PCI Express Base Specification Revision 3.0" says, "the software must wait for at least 1 second to judge device is broken after Data Link Layer State Changed Event". Therefore, I send a patch that drops DLLLA checking and adds 1 second wait. Signed-off-by: Naoki Yanagimoto --- -- Since I don't subscribe ML, please Cc me if you have any comment. Thanks, Naoki Yanagimoto -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff -uprN -X a/Documentation/dontdiff a/drivers/pci/hotplug/pciehp_ctrl.c b/drivers/pci/hotplug/pciehp_ctrl.c --- a/drivers/pci/hotplug/pciehp_ctrl.c 2011-06-21 12:25:46.000000000 +0900 +++ b/drivers/pci/hotplug/pciehp_ctrl.c 2011-07-04 17:36:55.000000000 +0900 @@ -206,6 +206,9 @@ static int board_added(struct slot *p_sl if (PWR_LED(ctrl)) pciehp_green_led_blink(p_slot); + /* Wait for ~1 second */ + msleep(1000); + /* Check link training status */ retval = pciehp_check_link_status(ctrl); if (retval) { diff -uprN -X a/Documentation/dontdiff a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c --- a/drivers/pci/hotplug/pciehp_hpc.c 2011-06-21 12:25:46.000000000 +0900 +++ b/drivers/pci/hotplug/pciehp_hpc.c 2011-07-04 17:36:55.000000000 +0900 @@ -241,52 +241,11 @@ static int pcie_write_cmd(struct control return retval; } -static inline int check_link_active(struct controller *ctrl) -{ - u16 link_status; - - if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) - return 0; - return !!(link_status & PCI_EXP_LNKSTA_DLLLA); -} - -static void pcie_wait_link_active(struct controller *ctrl) -{ - int timeout = 1000; - - if (check_link_active(ctrl)) - return; - while (timeout > 0) { - msleep(10); - timeout -= 10; - if (check_link_active(ctrl)) - return; - } - ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); -} - int pciehp_check_link_status(struct controller *ctrl) { u16 lnk_status; int retval = 0; - /* - * Data Link Layer Link Active Reporting must be capable for - * hot-plug capable downstream port. But old controller might - * not implement it. In this case, we wait for 1000 ms. - */ - if (ctrl->link_active_reporting){ - /* Wait for Data Link Layer Link Active bit to be set */ - pcie_wait_link_active(ctrl); - /* - * We must wait for 100 ms after the Data Link Layer - * Link Active bit reads 1b before initiating a - * configuration access to the hot added device. - */ - msleep(100); - } else - msleep(1000); - retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); if (retval) { ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");