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Fri, 8 Nov 2024 21:48:57 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 2/7] irqchip/gic-v3-its: Bypass iommu_cookie if desc->msi_iova is preset Date: Fri, 8 Nov 2024 21:48:47 -0800 Message-ID: <4e675b8ae803a478d10e675407ee1ff5f1f65890.1731130093.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|SN7PR12MB7936:EE_ X-MS-Office365-Filtering-Correlation-Id: 06986a8a-70ad-459e-1c8e-08dd00823862 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 1jTsxvCDGd/a+9zyaIoGl2ei6eED4I4AhNSdgS76MOaORRekaXizy6KBOTxn3QMdZ/7X1Dd2gNFje1lbjTPbGF3NUGLbalEk+pjvxMRG+6uVQViukkvsAzn0a8mxSbs2XEVxyEYu9oAGb6r2pEaPJOYgr6jSTU35fg8KYEPNv/zchhXaODHS01I3Sq1RFGHSrKGPYSZ504eU5i2zWY5Fl1PwOqEGFuvejgjeITJJZfwUdVROIdiv7Bv93jXCKs+DaJFctp8W32uK7k8F6Yr2iOiBj0bHmDfk3gvGuri6EmFl1BWmtDhxeWda/v2gw9V8tJajrFaPseRV1mnUOFVNYbgMKqIKCVYZVzNkYZfWrGcQA716xHrhcb2HwTlQsStkTxaA/SJ7AsPi9xItWBxVZ9x8mIzjUmhxUvaMoufaPvUTib2AcHg1zntP8Fc9FitIp7dlhvWSQDmiHFspCa66xATzuCRWizrfMX0np+8gliL6ofweQLyUtbGfqg1YSlODxopEOVdiSWrTeTLguTjcSe5u9bTW45PxZpC4eU/Sukb2scS+rXHowSrLk9hjYlokoxF+GdFZXgOidHRFoJkvauDyIpCJEEjkwYQN/SOs6sCUr2iclNIF10VMlLnap/dzMYfUgMH9q2IVAQQ3tZTuBrIt9Se8VhnlrbB4h8BeEl/yjUZSphpj18g7l0DL5T789rjuG2Kswvpxj+7iBb80ZSejQ/5lB2jsjjOFJ+EmuK9Z1AUS1kydJCT+0zvJzUMWzrtz9kW4/Gk94eF90UqH3OhBBUC0EpueEl70CN4j/8rTRo1IijbBBSQzJxlv8E5tfJYUygS+cmb9OE7IJVjhn+byWJq2eHHB3s3x5mkvLRBI/x8sYQk3EktZCGynkGmrwCcJkoWS0M2wFNTGfv04GXtNBfUDZxmiM/PahMPKgXlSV4He5c31icSH2G3hAqrzoxt1Ekd7x9K9d2PIhTuxQSePcwl8WF05wQeVBooFB4ekVYWB/B2JooryOeLI+LLyPtY0W+lesSv2LkFo59pSn8UzBpI2IvLWew09rSGg7aYY0gKmXNFUdc0fCcozqc96zZU0cBHFmHpyoiA4HY1ahI/0yrnV0W57ex+ypfxWzBNHjLHSpuFIKf3VAtaYFteAVWitiRRb4YQXo/NhAIfBUS4YzNwqx12DxeED4aKaYMtIPzdXv2qGSlLYvsvOEPBDywtx+mhjXQNGBuxLn7+Q+zm4DfG6fBNr+/jnMtux+tVukeeTAiiyEYkNAh2IovaA3BaDCv+s7ZInuYM/BFwYkO4OL8n+1vFy2baiZa1TJoA/BrsXh1rOJMkjlhc33J6soGbMPAF5An2l22BP3/6e3uL5Cd10GVaW4/9O3kRYaFTTjBOKvrxtE3J0qvAsBZPAvy174IorYnyRiLAlkzcmjQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:04.6618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 06986a8a-70ad-459e-1c8e-08dd00823862 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7936 Now struct msi_desc can carry a preset IOVA for MSI doorbell address. This is typically preset by user space when engaging a 2-stage translation. So, use the preset IOVA instead of kernel-level IOVA allocations in dma-iommu. Signed-off-by: Nicolin Chen --- drivers/irqchip/irq-gic-v3-its.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index ab597e74ba08..bc1768576546 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1723,6 +1723,8 @@ static u64 its_irq_get_msi_base(struct its_device *its_dev) static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct its_device *its_dev = irq_data_get_irq_chip_data(d); + struct msi_desc *desc = irq_data_get_msi_desc(d); + dma_addr_t iova = msi_desc_get_iova(desc); struct its_node *its; u64 addr; @@ -1733,7 +1735,13 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) msg->address_hi = upper_32_bits(addr); msg->data = its_get_event_id(d); - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg); + /* Bypass iommu_dma_compose_msi_msg if msi_iova is preset */ + if (iova == PHYS_ADDR_MAX) { + iommu_dma_compose_msi_msg(desc, msg); + } else { + msg->address_lo = lower_32_bits(iova); + msg->address_hi = upper_32_bits(iova); + } } static int its_irq_set_irqchip_state(struct irq_data *d, @@ -3570,6 +3578,7 @@ static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, { msi_alloc_info_t *info = args; struct its_device *its_dev = info->scratchpad[0].ptr; + dma_addr_t iova = msi_desc_get_iova(info->desc); struct its_node *its = its_dev->its; struct irq_data *irqd; irq_hw_number_t hwirq; @@ -3580,9 +3589,13 @@ static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, if (err) return err; - err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev)); - if (err) - return err; + /* Bypass iommu_dma_prepare_msi if msi_iova is preset */ + if (iova == PHYS_ADDR_MAX) { + err = iommu_dma_prepare_msi(info->desc, + its->get_msi_base(its_dev)); + if (err) + return err; + } for (i = 0; i < nr_irqs; i++) { err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);