From patchwork Fri Apr 17 09:50:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Duc Dang X-Patchwork-Id: 6229951 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 65B749F1C4 for ; Fri, 17 Apr 2015 09:52:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7A4ED20382 for ; Fri, 17 Apr 2015 09:52:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7FFD72037D for ; Fri, 17 Apr 2015 09:52:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932070AbbDQJvy (ORCPT ); Fri, 17 Apr 2015 05:51:54 -0400 Received: from exprod5og122.obsmtp.com ([64.18.0.192]:56632 "EHLO mail-pd0-f175.google.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932274AbbDQJv0 (ORCPT ); Fri, 17 Apr 2015 05:51:26 -0400 Received: from mail-pd0-f175.google.com ([209.85.192.175]) (using TLSv1) by exprod5ob122.postini.com ([64.18.4.12]) with SMTP ID DSNKVTDXnlI+fL4hBIVa4Ji80eJEnTVTD7S2@postini.com; Fri, 17 Apr 2015 02:51:26 PDT Received: by pdbqd1 with SMTP id qd1so123241659pdb.2 for ; Fri, 17 Apr 2015 02:51:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=XcLKuXTmu/ZeiJGeGzQVP8kZcnEx+SIPLMNPG8bllc8=; b=Oj6/wewfa66+DsWKUUjqP7P73HwFkd9jBBc0QHEN8xiXgt7GQppxQxQBS8jQiuPzpx fh28pNRmz0vbP2P4x39NjzcjUZNOy2+vVLE0KEUyHxCDLaoG9dX5x3UyO2kxsJM2/I+Z Zf1t6cAvYFvjOfsYkGv4cGWagDAUeYL9aPJEp1eUCpoHO83JPhOzI6zNgPzSBO6k/H78 JBmkjUw11jy5mrO6uWPLFmGgqwrp6KfdbStf7rZWPZx8zVDraazx9JzoTTg+fXe8JaFh EQczjSGAECuhzUoLm8fCotFfDIU68/zIyI2rUhSsiY5/mwHdO6xE2d2+uMQ681dAOfQo kkvQ== X-Gm-Message-State: ALoCoQkvexpVwJ8/bU21As1n12tap6jEy0m/6Io4o8WM7qpTaRDhu8hF7EysIUeNUAXM3iIRqIgFUsQyVVVNfO36InqmfVHBoc2U6MOX93rdM4mwCSANnZ4Oj0gGhc4cLXrCkTrodsxqN1LV0Y+rPbGI6y1f1BIrJw== X-Received: by 10.66.136.48 with SMTP id px16mr4008951pab.89.1429264285683; Fri, 17 Apr 2015 02:51:25 -0700 (PDT) X-Received: by 10.66.136.48 with SMTP id px16mr4008939pab.89.1429264285605; Fri, 17 Apr 2015 02:51:25 -0700 (PDT) Received: from dhdang-Precision-WorkStation-T3400.amcc.com (67-207-112-226.static.wiline.com. [67.207.112.226]) by mx.google.com with ESMTPSA id tr6sm9656930pab.4.2015.04.17.02.51.24 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Apr 2015 02:51:24 -0700 (PDT) From: Duc Dang To: Bjorn Helgaas , Arnd Bergmann , Grant Likely , Liviu Dudau , Marc Zyngier Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tanmay Inamdar , Loc Ho , Feng Kan , Duc Dang Subject: [PATCH v4 3/4] documentation: dts: Add the device tree binding for APM X-Gene v1 PCIe MSI device tree node Date: Fri, 17 Apr 2015 02:50:09 -0700 Message-Id: <5022d14af2964be107c174180238b8661bc25b46.1429263201.git.dhdang@apm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: <20150415091655.02361cdc@arm.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The driver for this binding is under 'drivers/pci/host/pci-xgene-msi.c' Signed-off-by: Duc Dang Signed-off-by: Tanmay Inamdar --- .../devicetree/bindings/pci/xgene-pci-msi.txt | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xgene-pci-msi.txt diff --git a/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt b/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt new file mode 100644 index 0000000..0ffdcb3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt @@ -0,0 +1,63 @@ +* AppliedMicro X-Gene PCIe MSI interface + +Required properties: + +- compatible: should contain "apm,xgene1-msi" to identify the core. +- msi-controller: indicates that this is X-Gene1 PCIe MSI controller node +- reg: A list of physical base address and length for each set of controller + registers. +- interrupts: A list of interrupt outputs of the controller. + +Each PCIe node needs to have property msi-parent that points to msi controller node + +Examples: + +SoC DTSI: + + + MSI node: + msi@79000000 { + compatible = "apm,xgene1-msi"; + msi-controller; + reg = <0x00 0x79000000 0x0 0x900000>; + interrupts = < 0x0 0x10 0x4 + 0x0 0x11 0x4 + 0x0 0x12 0x4 + 0x0 0x13 0x4 + 0x0 0x14 0x4 + 0x0 0x15 0x4 + 0x0 0x16 0x4 + 0x0 0x17 0x4 + 0x0 0x18 0x4 + 0x0 0x19 0x4 + 0x0 0x1a 0x4 + 0x0 0x1b 0x4 + 0x0 0x1c 0x4 + 0x0 0x1d 0x4 + 0x0 0x1e 0x4 + 0x0 0x1f 0x4>; + }; + + + PCIe controller node with msi-parent property pointing to MSI node: + pcie0: pcie@1f2b0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ + 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; + ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ + 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; + dma-coherent; + clocks = <&pcie0clk 0>; + msi-parent= <&msi>; + };