PCI/x86 CPU Hangs: Need to enable CRS Software Visibility (Configuration Request Retry Status)

Commit Message

Rajat Jain Aug. 1, 2014, 12:09 p.m. UTC

Hello,

I'm using an Intel Haswell CPU (/proc/cpu at the end of mail). I have a PCIe endpoint (a PLX 8713 NT bridge) that will take a long time to initialize itself after a reset. In accordance with the PCIe spec, the device responds with the CRS when the kernel tries to enumerate the endpoint, trying to indicate that the device is not yet ready.
[Ref: PCIe spec V3.0, pg119, pg127 for "Configuration Request Retry Status") 

This results in a CPU hang because the CPU root port goes into an endless cycle of retries, as the CRS Software Visibility is not enabled:
[Ref commit ad7edfe "[PCI] Do not enable CRS Software Visibility by default" by Linus]

The problem goes away if I enable the CRS software visibility and I see that the kernel moves on after timing out on that device:
pci 0000:30:00.0 id reading try 50 times with interval 20 ms to get ffff0001

Thus in a nutshell I want to enable the CRS Software visibility flag for my platform. From the commit log of the above commit, I'm trying to understand what would be the best way to do it. When the commit log says we should use white list for systems for which CRS should be enabled, and introduce something like pcibios_enable_crs(), do we mean something like this (suggestive patch only)?

---
 arch/x86/pci/common.c |   18 ++++++++++++++++++
 drivers/pci/pci.c     |    5 +++++
 drivers/pci/probe.c   |    2 ++
 include/linux/pci.h   |    1 +
 4 files changed, 26 insertions(+)

Patch

diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 81ec592..81b961d 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -634,6 +634,24 @@  char * __init pcibios_setup(char *str)
 	return str;
 }
 
+static const struct pci_device_id crs_whitelist[] = {
+	{ PCI_VDEVICE(INTEL, 0x2f00), },
+	{ PCI_VDEVICE(INTEL, 0x2f02), },
+	{ },
+};
+
+void pcibios_enable_crs(struct pci_dev *dev)
+{
+	if (!pci_is_pcie(dev) ||
+	    pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
+		return;
+
+	/* Enable CRS Software visibility only for whitelisted systems */
+	if (pci_match_id(crs_whitelist, dev))
+		pcie_capability_set_word(dev, PCI_EXP_RTCTL,
+					 PCI_EXP_RTCTL_CRSSVE);
+}
+
 unsigned int pcibios_assign_all_busses(void)
 {
 	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 3387c5e..982e8b1 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2685,6 +2685,11 @@  char * __weak __init pcibios_setup(char *str)
 	return str;
 }
 
+void __weak pcibios_enable_crs(struct pci_dev *dev)
+{
+	/* Do nothing by default, and let platforms decide for themselves */
+}
+
 /**
  * pcibios_set_master - enable PCI bus-mastering for device dev
  * @dev: the PCI device to enable
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 1aa058e..a4c50f7 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -801,6 +801,8 @@  int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
 			      bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
 
+	pcibios_enable_crs(dev);
+
 	if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
 	    !is_cardbus && !broken) {
 		unsigned int cmax;
diff --git a/include/linux/pci.h b/include/linux/pci.h
index dbe746f..8ac0b31 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -723,6 +723,7 @@  void pcibios_fixup_bus(struct pci_bus *);
 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
 /* Architecture-specific versions may override this (weak) */
 char *pcibios_setup(char *str);
+void pcibios_enable_crs(struct pci_dev *dev);
 
 /* Used only when drivers/pci/setup.c is used */
 resource_size_t pcibios_align_resource(void *, const struct resource *,