[RFC] PCI: designware: missing *config* reg space

Commit Message

Murali Karicheri April 27, 2015, 8:27 p.m. UTC

All,

I would like to take action to resolve the following print message 
thrown by PCI designware core driver when kernel boots up on Keystone.

[    0.415778] keystone-pcie 21801000.pcie: missing *config* reg space

As per DT documentation introduced by commit 
4dd964df36d0e548e1806ec2ec275b62d4dc46e8 "PCI: designware: Look for 
configuration space in 'reg', not 'ranges'

This is introduced to stop abusing the range property for defining 
resource for config space. However if the device binding doesn't have
reg-name = "config" defined, this throws out an unnecessary log message
at boot which seems to me not right. AFAIK, reg-names is not mandatory.
config space address in Keystone case is defined using index. So for
keystone this needs to be fixed.

I propose to add the following check in the designware code to address
this. Keystone uses an older version of the Designware IP and doesn't 
have the ATU support. So va_cfg0_base and va_cfg1_base are already set 
up in ks_dw_pcie_host_init() before calling dw_pcie_host_init() and 
points to the remote config space address (both same for keystone). I 
think for other DW drivers, these variables are NULL. So add a check and 
avoid this error message for Keystone. Any comments?


                 pp->cfg1_size = resource_size(cfg_res)/2;
@@ -372,7 +376,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
                 pp->cfg0_mod_base = of_read_number(addrp, ns);
                 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
         } else {
-               dev_err(pp->dev, "missing *config* reg space\n");
+               if (!pp->va_cfg0_base && !pp->va_cfg1_base)
+                       dev_err(pp->dev, "missing *config* reg space\n");
         }

Patch

--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -348,7 +348,7 @@  int dw_pcie_host_init(struct pcie_port *pp)
         struct platform_device *pdev = to_platform_device(pp->dev);
         struct of_pci_range range;
         struct of_pci_range_parser parser;
-       struct resource *cfg_res;
+       struct resource *cfg_res = NULL;
         u32 val, na, ns;
         const __be32 *addrp;
         int i, index, ret;
@@ -359,7 +359,11 @@  int dw_pcie_host_init(struct pcie_port *pp)
         of_property_read_u32(np, "#address-cells", &na);
         ns = of_n_size_cells(np);

-       cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 
"config");
+       if (!pp->va_cfg0_base && !pp->va_cfg0_base)
+               cfg_res = platform_get_resource_byname(pdev,
+                                                      IORESOURCE_MEM,
+                                                      "config");
+
         if (cfg_res) {
                 pp->cfg0_size = resource_size(cfg_res)/2;