From patchwork Fri May 15 02:09:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suravee Suthikulpanit X-Patchwork-Id: 6410651 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 29EF79F1CC for ; Fri, 15 May 2015 02:09:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 124AF2047D for ; Fri, 15 May 2015 02:09:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A423C20499 for ; Fri, 15 May 2015 02:09:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753353AbbEOCJa (ORCPT ); Thu, 14 May 2015 22:09:30 -0400 Received: from mail-bn1bon0116.outbound.protection.outlook.com ([157.56.111.116]:59067 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753276AbbEOCJ3 (ORCPT ); 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Thu, 14 May 2015 22:09:16 -0400 (EDT) Received: from SATLEXDAG05.amd.com (10.181.40.11) by satlvexedge01.amd.com (10.177.96.28) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 14 May 2015 21:09:23 -0500 Received: from [127.0.0.1] (10.180.168.240) by satlexdag05.amd.com (10.181.40.11) with Microsoft SMTP Server id 14.3.195.1; Thu, 14 May 2015 22:09:16 -0400 Message-ID: <5555553F.9070608@amd.com> Date: Thu, 14 May 2015 21:09:03 -0500 From: Suravee Suthikulanit User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Lorenzo Pieralisi , , , "Bjorn Helgaas" CC: Arnd Bergmann , Will Deacon , "Liviu Dudau" , Krzysztof Halasa , "Phil Edworthy" , Jason Gunthorpe , Jingoo Han , "Russell King" , Lucas Stach , "Simon Horman" , Minghuan Lian , Murali Karicheri , Tanmay Inamdar , Kishon Vijay Abraham I , Thierry Reding , Thomas Petazzoni , Jayachandran C Subject: Re: [RFC/RFT PATCH 2/2] ARM64: kernel: pci: implement PCI device resources claiming References: <1431614537-16136-1-git-send-email-lorenzo.pieralisi@arm.com> <1431614537-16136-2-git-send-email-lorenzo.pieralisi@arm.com> In-Reply-To: <1431614537-16136-2-git-send-email-lorenzo.pieralisi@arm.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; 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H:atltwp02.amd.com; FPR:; SPF:None; MLV:sfv; MX:1; A:1; LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR02MB1117; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:CY1PR02MB1117; BCL:0; PCL:0; RULEID:; SRVR:CY1PR02MB1117; X-Forefront-PRVS: 0577AD41D6 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2015 02:09:19.5598 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96; Ip=[165.204.84.222]; Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR02MB1117 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 5/14/2015 9:42 AM, Lorenzo Pieralisi wrote: > When a device is scanned and added to the PCI bus, its resources > should be claimed to validate the BARs configuration and to assign > them a parent resource so that the resource hierarchy can be sanity > checked. > > This patch adds code that carries out PCI device resources claiming to > the ARM64 pcibios_add_device implementation so that device resources > are claimed by the core PCI layer upon PCI device initialization on > ARM64 systems. > > Signed-off-by: Lorenzo Pieralisi > Cc: Arnd Bergmann > Cc: Will Deacon > Cc: Liviu Dudau > Cc: Bjorn Helgaas > --- > arch/arm64/kernel/pci.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c > index 4095379..c0a88ca 100644 > --- a/arch/arm64/kernel/pci.c > +++ b/arch/arm64/kernel/pci.c > @@ -43,8 +43,18 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res, > */ > int pcibios_add_device(struct pci_dev *dev) > { > + struct resource *res; > + int i; > + > dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); > > + for (i = 0; i < PCI_NUM_RESOURCES; i++) { > + res = &dev->resource[i]; > + if (res->parent || !res->flags) > + continue; > + pci_claim_resource(dev, i); > + } > + > return 0; > } > > Lorenzo/Bjorn, I have tested this patch on top of Jayachandran's V2 patch series (http://www.spinics.net/lists/linux-pci/msg40811.html) on AMD Seattle (w/ PROBE_ONLY and non-PROBE_ONLY mode), and your changes here works with additional changes below. It seems that when booting w/ PROBE_ONLY case, we need to call pci_read_bridge_bases() at some point before claiming the resources of devices underneath the bridge. This is needed to determine the bridge bases (i.e. bridge io, mmio and mmio_pref bases), and update bridge resources accordingly. ---- BEGIN PATCH ----- u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); ---- END PATCH ----- I'm not sure if this is the best place to be reading the bridge bases. I guess we should be able to do this when adding bridge devices. Thanks, Suravee --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index c0a88ca..57be6aa 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -48,6 +48,11 @@ int pcibios_add_device(struct pci_dev *dev) dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); + if (pci_has_flag(PCI_PROBE_ONLY) && + !pci_is_root_bus(dev->bus) && + !pci_bridge_bases_is_read(dev->bus)) + pci_read_bridge_bases(dev->bus); + for (i = 0; i < PCI_NUM_RESOURCES; i++) { res = &dev->resource[i]; if (res->parent || !res->flags) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 6675a7a..6cab8be 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -447,6 +447,13 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child) } } +bool pci_bridge_bases_is_read(struct pci_bus *bus) +{ + return (bus->resource[0]->start || + bus->resource[1]->start || + bus->resource[2]->start); +} + void pci_read_bridge_bases(struct pci_bus *child) { struct pci_dev *dev = child->self; diff --git a/include/linux/pci.h b/include/linux/pci.h index 353db8d..11c674d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -798,6 +798,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); unsigned int pci_scan_child_bus(struct pci_bus *bus); void pci_bus_add_device(struct pci_dev *dev); void pci_read_bridge_bases(struct pci_bus *child); +bool pci_bridge_bases_is_read(struct pci_bus *bus); struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);