[v4,01/25] PCI: Add PCI_ERROR_RESPONSE and it's related definitions

Commit Message

Naveen Naidu Nov. 18, 2021, 2:03 p.m. UTC

An MMIO read from a PCI device that doesn't exist or doesn't respond
causes a PCI error. There's no real data to return to satisfy the
CPU read, so most hardware fabricates ~0 data.

Add a PCI_ERROR_RESPONSE definition for that and use it where
appropriate to make these checks consistent and easier to find.

Also add helper definitions PCI_SET_ERROR_RESPONSE and
PCI_POSSIBLE_ERROR to make the code more readable.

Suggested-by: Bjorn Helgaas <[e-mail]>
Reviewed-by: Pali Rohár <[e-mail]>
Signed-off-by: Naveen Naidu <[e-mail]>
---
 include/linux/pci.h | 9 +++++++++
 1 file changed, 9 insertions(+)

Patch

diff --git a/include/linux/pci.h b/include/linux/pci.h
index 18a75c8e615c..0ce26850470e 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -154,6 +154,15 @@  enum pci_interrupt_pin {
 /* The number of legacy PCI INTx interrupts */
 #define PCI_NUM_INTX	4
 
+/*
+ * Reading from a device that doesn't respond typically returns ~0.  A
+ * successful read from a device may also return ~0, so you need additional
+ * information to reliably identify errors.
+ */
+#define PCI_ERROR_RESPONSE		(~0ULL)
+#define PCI_SET_ERROR_RESPONSE(val)	(*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
+#define PCI_POSSIBLE_ERROR(val)		((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
+
 /*
  * pci_power_t values must match the bits in the Capabilities PME_Support
  * and Control/Status PowerState fields in the Power Management capability.