From patchwork Thu Jul 16 19:13:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 6810571 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C84A59F380 for ; Thu, 16 Jul 2015 19:14:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CD09C2060A for ; Thu, 16 Jul 2015 19:14:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8EE10205E6 for ; Thu, 16 Jul 2015 19:14:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754272AbbGPTOU (ORCPT ); Thu, 16 Jul 2015 15:14:20 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:58133 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753436AbbGPTOT (ORCPT ); Thu, 16 Jul 2015 15:14:19 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t6GJDY9W000400; Thu, 16 Jul 2015 14:13:34 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t6GJDYJ2011178; Thu, 16 Jul 2015 14:13:34 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Thu, 16 Jul 2015 14:13:08 -0500 Received: from [158.218.101.213] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t6GJDX8m007981; Thu, 16 Jul 2015 14:13:33 -0500 Message-ID: <55A80262.2010401@ti.com> Date: Thu, 16 Jul 2015 15:13:38 -0400 From: Murali Karicheri Organization: Texas Instruments User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Bjorn Helgaas CC: , , , Russell King , Arnd Bergmann , Jason Gunthorpe Subject: Re: [PATCH v1] ARM: pci: add call to pcie_bus_configure_settings() References: <1401297293-3950-1-git-send-email-m-karicheri2@ti.com> <20150516140230.GF31666@google.com> In-Reply-To: <20150516140230.GF31666@google.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 05/16/2015 10:02 AM, Bjorn Helgaas wrote: > On Wed, May 28, 2014 at 01:14:53PM -0400, Murali Karicheri wrote: >> Call pcie_bus_configure_settings on ARM, like for other platforms. >> pcie_bus_configure_settings makes sure the MPS across the bus is >> uniform and provides the ability to tune the MRSS and MPS to higher >> performance values. This is particularly important for embedded where >> there is no firmware to program these PCI-E settings for the OS. >> >> Signed-off-by: Murali Karicheri >> >> CC: Russell King >> CC: Bjorn Helgaas >> CC: Arnd Bergmann >> CC: Jason Gunthorpe >> CC: Santosh Shilimkar >> --- >> - Fixed comments against initial version >> arch/arm/kernel/bios32.c | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> >> diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c >> index 16d43cd..17a26c1 100644 >> --- a/arch/arm/kernel/bios32.c >> +++ b/arch/arm/kernel/bios32.c >> @@ -545,6 +545,18 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw) >> */ >> pci_bus_add_devices(bus); >> } >> + >> + list_for_each_entry(sys, &head, node) { >> + struct pci_bus *bus = sys->bus; >> + >> + /* Configure PCI Express settings */ >> + if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { >> + struct pci_bus *child; >> + >> + list_for_each_entry(child, &bus->children, node) >> + pcie_bus_configure_settings(child); > > This patch (8b5742ad156d ("ARM/PCI: Call pcie_bus_configure_settings() to > set MPS")) has been upstream since v3.16-rc1, but I think we goofed. > > The MPS configuration should be done *before* pci_bus_add_devices(). After > pci_bus_add_devices(), drivers may be bound to devices, and the PCI core > shouldn't touch device configuration while a driver owns the device. > > Looking at the code, it seems like it would have been simpler to do this in > the existing loop: > > list_for_each_entry(sys, &head, node) { > struct pci_bus *bus = sys->bus; > > if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { > pci_bus_size_bridges(bus); > pci_bus_assign_resources(bus); > list_for_each_entry(child, &bus->children, node) > pcie_bus_configure_settings(child); > } > > pci_bus_add_devices(bus); > } > > so maybe there's some reason I'm not aware of for not doing it that way? Bjorn, This one has escaped my radar and I found it recently while I was searching for something else. I can't recall why this was not done this way. However I have tried the below code on Keystone and it works fine. */ @@ -530,25 +531,15 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw) * Assign resources. */ pci_bus_assign_resources(bus); - } + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + } /* * Tell drivers about devices found. */ pci_bus_add_devices(bus); } - - list_for_each_entry(sys, &head, node) { - struct pci_bus *bus = sys->bus; - - /* Configure PCI Express settings */ - if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { - struct pci_bus *child; - - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - } - } } The SATA comes up fine and ahci is able to override the mrrs value as shown by the log below. [ 1.581526] ahci 0001:01:00.0: limiting MRRS to 256 [ 1.586521] ahci 0001:01:00.0: AHCI 0001.0000 32 slots 2 ports 6 Gbps 0x3 impl SATA mode [ 1.594604] ahci 0001:01:00.0: flags: 64bit ncq sntf led only pmp fbs pio slum part sxs [ 1.603772] scsi host0: ahci [ 1.606976] scsi host1: ahci [ If you are fine, I can send a patch for this. Please confirm. Murali > >> + } >> + } >> } >> >> #ifndef CONFIG_PCI_HOST_ITE8152 >> -- >> 1.7.9.5 >> diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index fcbbbb1..17efde7 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -520,7 +520,8 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw) list_for_each_entry(sys, &head, node) { struct pci_bus *bus = sys->bus; - if (!pci_has_flag(PCI_PROBE_ONLY)) { + if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { + struct pci_bus *child; /* * Size the bridge windows.