From patchwork Wed Mar 29 11:34:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Gonzalez X-Patchwork-Id: 9651381 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9C6B3602C8 for ; Wed, 29 Mar 2017 11:37:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D55E20499 for ; Wed, 29 Mar 2017 11:37:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6180C26E4F; Wed, 29 Mar 2017 11:37:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AF94320499 for ; Wed, 29 Mar 2017 11:37:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755869AbdC2LgC (ORCPT ); Wed, 29 Mar 2017 07:36:02 -0400 Received: from mail1.bemta12.messagelabs.com ([216.82.251.16]:23604 "EHLO mail1.bemta12.messagelabs.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756001AbdC2Lfc (ORCPT ); Wed, 29 Mar 2017 07:35:32 -0400 Received: from [216.82.251.38] by server-16.bemta-12.messagelabs.com id D0/37-28713-00C9BD85; Wed, 29 Mar 2017 11:35:28 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjleJIrShJLcpLzFFi42I5fN1ile7/2bc jDHoPGFjsWLqZyWL+kXOsFq/OrGWz2PT4GqvF5V1z2CzOzjvOZnFgaTuLxZvfL9gt/t75x2Zx 8MMTVouWpzMYLTZvmsrswOPRP3sKm8eaeWsYPfrXfWb12LSqk83j3blz7B6bl9R7fN4kF8Aex ZqZl5RfkcCa8eHIXOaCL+YV1xd7NDD+0eti5OIQEljGKLHozRPmLkZODmEBe4kvB06wg9hsAi YSN++fYwGxRQSKJL6/msMK0sAscJhZYs+l62BFQgLOEt9bfrKB2LxA9qSZy4BsDg4WAVWJKxc yQcKiAgkSF/9MYYUoEZQ4OfMJ2ExOAReJS8dPMYLYzAL6Ek1b5zBD2PIS299C2EIC2hLvNy4G 65UQUJCYOrmVeQIj/ywko2YhaZ+FpH0BI/MqRo3i1KKy1CJdY0O9pKLM9IyS3MTMHF1DQyO93 NTi4sT01JzEpGK95PzcTYzAWKlnYGDcwfjni+8hRkkOJiVR3hOGtyOE+JLyUyozEosz4otKc1 KLDzHKcHAoSfAemQWUEyxKTU+tSMvMAUYtTFqCg0dJhPcnSJq3uCAxtzgzHSJ1itGY49mJXW+ YOH71HHvDJMSSl5+XKiXOuwykVACkNKM0D24QLJlcYpSVEuZlZGBgEOIpSC3KzSxBlX/FKM7B qCTMOwNkCk9mXgncvldApzABnSJucwvklJJEhJRUA6Pq3l8Z4uq710fan2l7deh56Zp9h4KLp m0vSNQ58V+jw6eRMUKLX4np5CF+F239iaxHVgef8ef+rns2SfWX0IHTwjdCVty4HHTNxjD50v kH7lk9ikpeWSd530xzTvxe/GKW8qvEc19+cgY+FH90ZeqZ06yMNxQWOtXMaepluNX3MltEhWP F2kQlluKMREMt5qLiRAAdl4x1IQMAAA== X-Env-Sender: Marc_Gonzalez@sigmadesigns.com X-Msg-Ref: server-9.tower-163.messagelabs.com!1490787325!125039337!1 X-Originating-IP: [195.215.56.170] X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 86426 invoked from network); 29 Mar 2017 11:35:27 -0000 Received: from 195-215-56-170-static.dk.customer.tdc.net (HELO CPH-EX1.SDESIGNS.COM) (195.215.56.170) by server-9.tower-163.messagelabs.com with AES128-SHA encrypted SMTP; 29 Mar 2017 11:35:27 -0000 Received: from [172.27.0.114] (172.27.0.114) by CPH-EX1.sdesigns.com (192.168.10.36) with Microsoft SMTP Server (TLS) id 14.3.294.0; Wed, 29 Mar 2017 13:35:25 +0200 Subject: [PATCH v3 2/2] PCI: Add tango PCIe host bridge support From: Marc Gonzalez To: Bjorn Helgaas , Marc Zyngier , Thomas Gleixner CC: Robin Murphy , Lorenzo Pieralisi , Liviu Dudau , David Laight , linux-pci , Linux ARM , Thibaud Cornic , Phuong Nguyen , LKML , DT , Mason References: <5309e718-5813-5b79-db57-9d702b50d0f9@sigmadesigns.com> Message-ID: <65114e62-7458-b6f7-327c-f07a5096a452@sigmadesigns.com> Date: Wed, 29 Mar 2017 13:34:45 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:51.0) Gecko/20100101 Firefox/51.0 SeaMonkey/2.48 MIME-Version: 1.0 In-Reply-To: <5309e718-5813-5b79-db57-9d702b50d0f9@sigmadesigns.com> X-Originating-IP: [172.27.0.114] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This driver is used to work around HW bugs in the controller. Note: the controller does NOT support the following features. Legacy PCI interrupts IO space Signed-off-by: Marc Gonzalez Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/tango-pcie.txt | 33 +++++++++ drivers/pci/host/Kconfig | 7 ++ drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-tango.c | 150 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 191 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/tango-pcie.txt b/Documentation/devicetree/bindings/pci/tango-pcie.txt new file mode 100644 index 000000000000..f8e150ec41d8 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/tango-pcie.txt @@ -0,0 +1,33 @@ +Sigma Designs Tango PCIe controller + +Required properties: + +- compatible: "sigma,smp8759-pcie" +- reg: address/size of PCI configuration space, and pcie_reg +- bus-range: defined by size of PCI configuration space +- device_type: "pci" +- #size-cells: <2> +- #address-cells: <3> +- #interrupt-cells: <1> +- ranges: translation from system to bus addresses +- interrupts: spec for misc interrupts and MSI +- msi-controller + +Example: + + pcie@2e000 { + compatible = "sigma,smp8759-pcie"; + reg = <0x50000000 SZ_64M>, <0x2e000 0x100>; + bus-range = <0 63>; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + #interrupt-cells = <1>; + /* http://elinux.org/Device_Tree_Usage#PCI_Address_Translation */ + /* BUS_ADDRESS(3) CPU_PHYSICAL(1) SIZE(2) */ + ranges = <0x02000000 0x0 0x04000000 0x54000000 0x0 SZ_192M>; + interrupts = + <54 IRQ_TYPE_LEVEL_HIGH>, /* misc interrupts */ + <55 IRQ_TYPE_LEVEL_HIGH>; /* MSI */ + msi-controller; + }; diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index d7e7c0a827c3..8a622578a760 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -285,6 +285,13 @@ config PCIE_ROCKCHIP There is 1 internal PCIe port available to support GEN2 with 4 slots. +config PCIE_TANGO + tristate "Tango PCIe controller" + depends on ARCH_TANGO && PCI_MSI && OF + select PCI_HOST_COMMON + help + Say Y here to enable PCIe controller support on Tango SoC. + config VMD depends on PCI_MSI && X86_64 tristate "Intel Volume Management Device Driver" diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index 084cb4983645..fc7ea90196f3 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -32,4 +32,5 @@ obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o +obj-$(CONFIG_PCIE_TANGO) += pcie-tango.o obj-$(CONFIG_VMD) += vmd.o diff --git a/drivers/pci/host/pcie-tango.c b/drivers/pci/host/pcie-tango.c index e88850983a1d..dbc2663486b5 100644 --- a/drivers/pci/host/pcie-tango.c +++ b/drivers/pci/host/pcie-tango.c @@ -192,3 +192,153 @@ static int tango_msi_probe(struct platform_device *pdev, struct tango_pcie *pcie return 0; } + +/*** HOST BRIDGE SUPPORT ***/ + +static int smp8759_config_read(struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 *val) +{ + int ret; + struct pci_config_window *cfg = bus->sysdata; + struct tango_pcie *pcie = dev_get_drvdata(cfg->parent); + + /* + * QUIRK #1 + * Reads in configuration space outside devfn 0 return garbage. + */ + if (devfn != 0) { + *val = ~0; /* Is this required even if we return an error? */ + return PCIBIOS_FUNC_NOT_SUPPORTED; /* Error seems appropriate */ + } + + /* + * QUIRK #2 + * The root complex advertizes a fake BAR, which is used to filter + * bus-to-system requests. Hide it from Linux. + */ + if (where == PCI_BASE_ADDRESS_0 && bus->number == 0) { + *val = 0; /* 0 or ~0 to hide the BAR from Linux? */ + return PCIBIOS_SUCCESSFUL; /* Should we return error or success? */ + } + + /* + * QUIRK #3 + * Unfortunately, config and mem spaces are muxed. + * Linux does not support such a setting, since drivers are free + * to access mem space directly, at any time. + * Therefore, we can only PRAY that config and mem space accesses + * NEVER occur concurrently. + */ + writel_relaxed(1, pcie->mux); + ret = pci_generic_config_read(bus, devfn, where, size, val); + writel_relaxed(0, pcie->mux); + + return ret; +} + +static int smp8759_config_write(struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 val) +{ + int ret; + struct pci_config_window *cfg = bus->sysdata; + struct tango_pcie *pcie = dev_get_drvdata(cfg->parent); + + writel_relaxed(1, pcie->mux); + ret = pci_generic_config_write(bus, devfn, where, size, val); + writel_relaxed(0, pcie->mux); + + return ret; +} + +static struct pci_ecam_ops smp8759_ecam_ops = { + .bus_shift = 20, + .pci_ops = { + .map_bus = pci_ecam_map_bus, + .read = smp8759_config_read, + .write = smp8759_config_write, + } +}; + +static const struct of_device_id tango_pcie_ids[] = { + { .compatible = "sigma,smp8759-pcie" }, + { /* sentinel */ }, +}; + +static void smp8759_init(struct tango_pcie *pcie, void __iomem *base) +{ + pcie->mux = base + 0x48; + pcie->msi_status = base + 0x80; + pcie->msi_mask = base + 0xa0; + pcie->msi_doorbell = 0xa0000000 + 0x2e07c; +} + +static int tango_pcie_probe(struct platform_device *pdev) +{ + int ret; + void __iomem *base; + struct resource *res; + struct tango_pcie *pcie; + struct device *dev = &pdev->dev; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + platform_set_drvdata(pdev, pcie); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + if (of_device_is_compatible(dev->of_node, "sigma,smp8759-pcie")) + smp8759_init(pcie, base); + + ret = tango_msi_probe(pdev, pcie); + if (ret) + return ret; + + return pci_host_common_probe(pdev, &smp8759_ecam_ops); +} + +static int tango_pcie_remove(struct platform_device *pdev) +{ + return tango_msi_remove(pdev); +} + +static struct platform_driver tango_pcie_driver = { + .probe = tango_pcie_probe, + .remove = tango_pcie_remove, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = tango_pcie_ids, + }, +}; + +module_platform_driver(tango_pcie_driver); + +#define VENDOR_SIGMA 0x1105 + +/* + * QUIRK #4 + * The root complex advertizes the wrong device class. + * Header Type 1 is for PCI-to-PCI bridges. + */ +static void tango_fixup_class(struct pci_dev *dev) +{ + dev->class = PCI_CLASS_BRIDGE_PCI << 8; +} +DECLARE_PCI_FIXUP_EARLY(VENDOR_SIGMA, PCI_ANY_ID, tango_fixup_class); + +/* + * QUIRK #5 + * Only transfers within the root complex BAR are forwarded to the host. + * By default, the DMA framework expects that + * PCI address 0x8000_0000 maps to system address 0x8000_0000 + * which is where DRAM0 is mapped. + */ +static void tango_fixup_bar(struct pci_dev *dev) +{ + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x80000000); +} +DECLARE_PCI_FIXUP_FINAL(VENDOR_SIGMA, PCI_ANY_ID, tango_fixup_bar);