From patchwork Wed Sep 7 20:22:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 9319873 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0E8DE6077F for ; Wed, 7 Sep 2016 20:22:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB4C72941F for ; Wed, 7 Sep 2016 20:22:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DFB2B29422; Wed, 7 Sep 2016 20:22:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3AF292941F for ; Wed, 7 Sep 2016 20:22:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757350AbcIGUWV (ORCPT ); Wed, 7 Sep 2016 16:22:21 -0400 Received: from mail-lf0-f42.google.com ([209.85.215.42]:34958 "EHLO mail-lf0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751260AbcIGUWT (ORCPT ); Wed, 7 Sep 2016 16:22:19 -0400 Received: by mail-lf0-f42.google.com with SMTP id l131so6675850lfl.2 for ; Wed, 07 Sep 2016 13:22:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:organization:user-agent :mime-version:content-transfer-encoding; bh=qE5H3M334rcjORxy3gAUJZttRiAYebOIJQLG6EajHmc=; b=g4j3DZpHkkkjq5u5ogdEjc6Md9MunYVoGiSLvRxKkp2o+RvSfPFc3imUYyHlOdowO9 x9dJGRYQmJbb8e+gxH29qlOLxgRDLqWGDeHo0PqArQM3T6mKkLtmPI/gSphVu8ZdqBb0 Lo99tNH6und+aXZCGdlgYzr7Al0dE+6KiE2rPSOs/c6ecnU0w6zvXzRLNgqfTy/ZjHO7 wzYXFBpeXi6w/fgVbsjGggM8rlX1VdczxCW1IZs6PmNBdLAgYyZ/YWaFKwAtShXe8+G9 iFF7BSLWYhMZN2A8JImpdtKhknqSYJdnQG85K22oyZ6LfN5knV9eaGEaixqvyn45zODU 8zeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:organization :user-agent:mime-version:content-transfer-encoding; bh=qE5H3M334rcjORxy3gAUJZttRiAYebOIJQLG6EajHmc=; b=IvgkEEDglHzlVBmgqERI9AVtAoBP6VvvmwLZjFhEwQ88/BEsw9J6u0zL/gxdzrb+bm 5CKcXUA+T9KOp/kYqTJR0hXGX4XO+FuMFkHQNZMZEYdDscdFGvZEdHoYF4ihrkVAcUaN ccmoKB+MQsNaBz78Tz5u/ekc9a5Y6Eas+nRwr+1PbyyUmIcj+kVnFEKcU7Ke2U5rRLz8 2X7OPQe2ldrk3H+thbGh6NhXktHawnoBsaWTnuXL57KnYuiq4SGv5y5Y/l0mmSJ7oXmz 1XWN8KmxGt5uirqOGQhie6DMh4efdl47hSOuCw+OkK5moMlcwe724EyBSrFWkobj9Z10 lZdg== X-Gm-Message-State: AE9vXwNHxpaU6wZDbT8/+o0nX4RRRzaWPc6zvrfQo+BAxZGHqiLErpaW9h5KSIWsFMwH5A== X-Received: by 10.25.215.150 with SMTP id q22mr426097lfi.98.1473279737548; Wed, 07 Sep 2016 13:22:17 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.84.216]) by smtp.gmail.com with ESMTPSA id e73sm6789264lji.31.2016.09.07.13.22.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Sep 2016 13:22:16 -0700 (PDT) From: Sergei Shtylyov To: horms@verge.net.au, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH] pcie-rcar: try setting PCIe speed to 5 GT/s at boot Date: Wed, 07 Sep 2016 23:22:14 +0300 Message-ID: <6896977.DKiraAXap6@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.10 (Linux/4.7.2-101.fc23.x86_64; KDE/4.14.20; x86_64; ; ) MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Grigory Kletsko Initially, the PCIe link speed is set up only at 2.5 GT/s. For better performance, we're trying to increase link speed to 5 GT/s. [Sergei Shtylyov: indented the macro definitions with tabs, renamed the SPCHG register bits for consistency, renamed the link speed field/values, fixed too long lines, fixed redundancy in clearing the MACSR register bits, fixed grammar/typos in the comments/messages, removed unrelated/useless changes, fixed bugs in rcar_rwm32() calls done to set the bits, removed unneeded braces, removed non-informative comment, reworded the patch summary/description.] Signed-off-by: Grigory Kletsko Signed-off-by: Sergei Shtylyov Acked-by: Simon Horman --- The patch is against the 'next' branch of Bjorn Helgaas' 'pci.git' repo. drivers/pci/host/pcie-rcar.c | 103 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: pci/drivers/pci/host/pcie-rcar.c =================================================================== --- pci.orig/drivers/pci/host/pcie-rcar.c +++ pci/drivers/pci/host/pcie-rcar.c @@ -48,6 +48,10 @@ #define CFINIT 1 #define PCIETSTR 0x02004 #define DATA_LINK_ACTIVE 1 +#define PCIEINTR 0x02008 +#define PCIEINTMAC (1 << 13) +#define PCIEINTER 0x0200C +#define PCIEINTMACE (1 << 13) #define PCIEERRFR 0x02020 #define UNSUPPORTED_REQUEST (1 << 4) #define PCIEMSIFR 0x02044 @@ -84,8 +88,21 @@ #define IDSETR1 0x011004 #define TLCTLR 0x011048 #define MACSR 0x011054 +#define SPCHG (1 << 5) +#define SPCHGFIN (1 << 4) +#define SPCHGSUC (1 << 7) +#define SPCHGFAIL (1 << 6) +#define LINK_SPEED (0xf << 16) +#define LINK_SPEED_2_5GTS (1 << 16) +#define LINK_SPEED_5_0GTS (2 << 16) #define MACCTLR 0x011058 +#define SPEED_CHANGE (1 << 24) #define SCRAMBLE_DISABLE (1 << 27) +#define MACINTENR 0x01106C +#define SPCHGFINE (1 << 4) +#define MACS2R 0x011078 +#define MACCGSPSETR 0x011084 +#define SPCNGRSN (1 << 31) /* R-Car H1 PHY */ #define H1_PCIEPHYADRR 0x04000c @@ -385,6 +402,51 @@ static int rcar_pcie_setup(struct list_h return 1; } +void rcar_pcie_force_speedup(struct rcar_pcie *pcie) +{ + u32 macsr; + + dev_info(pcie->dev, "Trying speed up to 5 GT/s\n"); + + if ((rcar_pci_read_reg(pcie, MACSR) & SPCHGFIN) || + (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE)) { + dev_err(pcie->dev, "Speed changing is in progress\n"); + return; + } + + if ((rcar_pci_read_reg(pcie, MACSR) & LINK_SPEED) == + LINK_SPEED_5_0GTS) { + dev_err(pcie->dev, "Current link speed is already 5 GT/s\n"); + return; + } + + if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != + LINK_SPEED_5_0GTS) { + dev_err(pcie->dev, + "Current max support link speed not 5 GT/s\n"); + return; + } + + /* Set target link speed to 5.0 GT/s */ + rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, + PCI_EXP_LNKSTA_CLS_5_0GB); + + /* Set speed change reason as intentional factor */ + rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); + + /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ + macsr = rcar_pci_read_reg(pcie, MACSR); + if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) + rcar_pci_write_reg(pcie, macsr, MACSR); + + /* Enable interrupt */ + rcar_rmw32(pcie, MACINTENR, SPCHGFINE, SPCHGFINE); + rcar_rmw32(pcie, PCIEINTER, PCIEINTMACE, PCIEINTMACE); + + /* Start link speed change */ + rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); +} + static int rcar_pcie_enable(struct rcar_pcie *pcie) { struct pci_bus *bus, *child; @@ -416,6 +478,9 @@ static int rcar_pcie_enable(struct rcar_ pci_bus_add_devices(bus); + /* Try setting 5 GT/s link speed */ + rcar_pcie_force_speedup(pcie); + return 0; } @@ -621,6 +686,44 @@ static irqreturn_t rcar_pcie_msi_irq(int struct rcar_msi *msi = &pcie->msi; unsigned long reg; + if (rcar_pci_read_reg(pcie, PCIEINTR) & PCIEINTMAC) { + dev_dbg(pcie->dev, "MAC interrupt received\n"); + + rcar_rmw32(pcie, MACSR, SPCHGFIN, SPCHGFIN); + + /* Disable this interrupt */ + rcar_rmw32(pcie, MACINTENR, SPCHGFINE, 0); + rcar_rmw32(pcie, PCIEINTER, PCIEINTMACE, 0); + + if (rcar_pci_read_reg(pcie, MACSR) & SPCHGFAIL) { + dev_err(pcie->dev, "Speed change failed\n"); + + rcar_rmw32(pcie, MACSR, SPCHGFAIL, SPCHGFAIL); + /* + * TODO: if speed change failed we need to enable + * "L0 enter" interrupt and set "speed change disabled" + * state. After L0 interrupt rising, we must clear it, + * wait for 200 ms and set "speed change enabled" state + * according to the R-Car Series, 2nd Generation User's + * Manual, section 50.3.9. + */ + return IRQ_HANDLED; + } + + if (rcar_pci_read_reg(pcie, MACSR) & SPCHGSUC) + rcar_rmw32(pcie, MACSR, SPCHGSUC, SPCHGSUC); + + /* Check speed */ + if ((rcar_pci_read_reg(pcie, MACSR) & LINK_SPEED) == + LINK_SPEED_5_0GTS) + dev_info(pcie->dev, "Current link speed now 5 GT/s\n"); + else + dev_info(pcie->dev, + "Current link speed now 2.5 GT/s\n"); + + return IRQ_HANDLED; + } + reg = rcar_pci_read_reg(pcie, PCIEMSIFR); /* MSI & INTx share an interrupt - we only handle MSI here */