From patchwork Mon Oct 29 07:01:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush ANAND X-Patchwork-Id: 1661421 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id D84C63FCF7 for ; Mon, 29 Oct 2012 07:02:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751553Ab2J2HCN (ORCPT ); Mon, 29 Oct 2012 03:02:13 -0400 Received: from eu1sys200aog110.obsmtp.com ([207.126.144.129]:35001 "EHLO eu1sys200aog110.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751661Ab2J2HCL (ORCPT ); Mon, 29 Oct 2012 03:02:11 -0400 Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob110.postini.com ([207.126.147.11]) with SMTP ID DSNKUI4p6nQL6HZjFefpJRyBNsfbcBpmeZ2v@postini.com; Mon, 29 Oct 2012 07:02:10 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5DC6D9E; Mon, 29 Oct 2012 06:53:46 +0000 (GMT) Received: from Webmail-ap.st.com (eapex1hubcas2.st.com [10.80.176.10]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 455CB988; Mon, 29 Oct 2012 07:01:59 +0000 (GMT) Received: from localhost (10.199.81.103) by Webmail-ap.st.com (10.80.176.7) with Microsoft SMTP Server (TLS) id 8.3.245.1; Mon, 29 Oct 2012 15:01:59 +0800 From: Pratyush Anand To: , , Cc: , , , , Pratyush Anand Subject: [PATCH 02/15] arm: Call pcie_bus_configure_settings for pcie devices Date: Mon, 29 Oct 2012 12:31:16 +0530 Message-ID: <6eff165d5aee88370855ff1cb9be2ff4be4ef50c.1351492562.git.pratyush.anand@st.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org There could be some device which will work only after adjusting their "Max Packet Size" and/or "Max Read Request Size". This modification will only be effective if proper 'pci=' bootargs is passed. Signed-off-by: Pratyush Anand --- arch/arm/kernel/bios32.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 2555250..62d603f 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -490,6 +490,18 @@ void __init pci_common_init(struct hw_pci *hw) struct pci_bus *bus = sys->bus; if (!pci_has_flag(PCI_PROBE_ONLY)) { + struct pci_bus *child; + + /* + * Set MPS and readrq size + */ + list_for_each_entry(child, &bus->children, node) { + struct pci_dev *self = child->self; + if (!self) + continue; + pcie_bus_configure_settings(child, + self->pcie_mpss); + } /* * Size the bridge windows. */