| Message ID | 969d4f083f445532bd1cdd98e3ce110574a461b0.1590534843.git.sathyanarayanan.kuppuswamy@linux.intel.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | Remove AER HEST table parser | expand |
On Tue, May 26, 2020 at 04:18:27PM -0700, sathyanarayanan.kuppuswamy@linux.intel.com wrote: > From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> > > pcie_ports_native is set only if user requests native handling > of PCIe capabilities via pcie_port_setup command line option. > User input takes precedence over _OSC based control negotiation > result. So consider the _OSC negotiated result only if > pcie_ports_native is unset. > > Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> > --- > drivers/acpi/pci_root.c | 26 ++++++++++++++------------ > 1 file changed, 14 insertions(+), 12 deletions(-) > > diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c > index 9e235c1a75ff..e0039ad3480a 100644 > --- a/drivers/acpi/pci_root.c > +++ b/drivers/acpi/pci_root.c > @@ -914,18 +914,20 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, > goto out_release_info; > > host_bridge = to_pci_host_bridge(bus->bridge); > - if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) > - host_bridge->native_pcie_hotplug = 0; > - if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) > - host_bridge->native_shpc_hotplug = 0; > - if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) > - host_bridge->native_aer = 0; > - if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) > - host_bridge->native_pme = 0; > - if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) > - host_bridge->native_ltr = 0; > - if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) > - host_bridge->native_dpc = 0; > + if (!pcie_ports_native) { > + if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) > + host_bridge->native_pcie_hotplug = 0; > + if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) > + host_bridge->native_shpc_hotplug = 0; > + if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) > + host_bridge->native_aer = 0; > + if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) > + host_bridge->native_pme = 0; > + if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) > + host_bridge->native_ltr = 0; > + if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) > + host_bridge->native_dpc = 0; > + } I like this, but what I had in mind was to *remove* the tests of pcie_ports_native elsewhere at the same time. For example, @@ -255,7 +255,7 @@ static bool pme_is_native(struct pcie_device *dev) const struct pci_host_bridge *host; host = pci_find_host_bridge(dev->port->bus); - return pcie_ports_native || host->native_pme; + return host->native_pme; } and @@ -221,7 +221,7 @@ int pcie_aer_is_native(struct pci_dev *dev) if (!dev->aer_cap) return 0; - return pcie_ports_native || host->native_aer; + return host->native_aer; } So I deferred these two _OSC-related things for now. We can work on this more in the next cycle. > /* > * Evaluate the "PCI Boot Configuration" _DSM Function. If it > -- > 2.17.1 >
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index 9e235c1a75ff..e0039ad3480a 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -914,18 +914,20 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, goto out_release_info; host_bridge = to_pci_host_bridge(bus->bridge); - if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) - host_bridge->native_pcie_hotplug = 0; - if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) - host_bridge->native_shpc_hotplug = 0; - if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) - host_bridge->native_aer = 0; - if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) - host_bridge->native_pme = 0; - if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) - host_bridge->native_ltr = 0; - if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) - host_bridge->native_dpc = 0; + if (!pcie_ports_native) { + if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) + host_bridge->native_pcie_hotplug = 0; + if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) + host_bridge->native_shpc_hotplug = 0; + if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) + host_bridge->native_aer = 0; + if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) + host_bridge->native_pme = 0; + if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) + host_bridge->native_ltr = 0; + if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) + host_bridge->native_dpc = 0; + } /* * Evaluate the "PCI Boot Configuration" _DSM Function. If it