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Mon, 8 Oct 2018 18:06:23 +0000 Received: from AM0PR04MB4290.eurprd04.prod.outlook.com ([fe80::3836:6416:4ebd:34ef]) by AM0PR04MB4290.eurprd04.prod.outlook.com ([fe80::3836:6416:4ebd:34ef%3]) with mapi id 15.20.1207.024; Mon, 8 Oct 2018 18:06:23 +0000 From: Leonard Crestez To: Shawn Guo , Lucas Stach , Richard Zhu CC: Lorenzo Pieralisi , Fabio Estevam , Stefan Agner , Marek Vasut , Ulf Hansson , Rob Herring , Mark Rutland , "linux-pm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-pci@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , dl-linux-imx , "kernel@pengutronix.de" , "linux-kernel@vger.kernel.org" Subject: [PATCH v2 4/4] ARM: dts: imx6sx: Add DISPLAY power domain support Thread-Topic: [PATCH v2 4/4] ARM: dts: imx6sx: Add DISPLAY power domain support Thread-Index: AQHUXzGf8guh/Nb5iEavRi81Wh8wzA== Date: Mon, 8 Oct 2018 18:06:23 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [95.76.156.53] x-mailer: git-send-email 2.17.1 x-clientproxiedby: AM6PR0102CA0011.eurprd01.prod.exchangelabs.com (2603:10a6:209:14::24) To AM0PR04MB4290.eurprd04.prod.outlook.com (2603:10a6:208:67::17) authentication-results: spf=none (sender IP is ) smtp.mailfrom=leonard.crestez@nxp.com; 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This makes it always on. From reference manual in section "10.4.1.4.1 Power Distribution": "Display domain - The DISPLAY domain contains GIS, CSI, PXP, LCDIF, PCIe, DCIC, and LDB. It is supplied by internal regulator." The current pd_pcie is actually only for PCIE_PHY, the PCIE ip block is actually inside the DISPLAY domain. Handle this by adding the pcie node in both power domains. Signed-off-by: Leonard Crestez --- arch/arm/boot/dts/imx6sx.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 95a3c1cb877d..b7f815d82d1b 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -778,10 +778,22 @@ #power-domain-cells = <0>; power-supply = <®_soc>; clocks = <&clks IMX6SX_CLK_GPU>; }; + pd_disp: power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + clocks = <&clks IMX6SX_CLK_PXP_AXI>, + <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_LCDIF1_PIX>, + <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_LCDIF2_PIX>, + <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_VADC>; + }; + pd_pci: power-domain@3 { reg = <3>; #power-domain-cells = <0>; power-supply = <®_pcie>; }; @@ -1196,10 +1208,11 @@ reg = <0x02218000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_PXP_AXI>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pxp-axi", "disp-axi"; + power-domains = <&pd_disp>; status = "disabled"; }; csi2: csi@221c000 { reg = <0x0221c000 0x4000>; @@ -1217,10 +1230,11 @@ interrupts = ; clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&pd_disp>; status = "disabled"; }; lcdif2: lcdif@2224000 { compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; @@ -1228,19 +1242,21 @@ interrupts = ; clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&pd_disp>; status = "disabled"; }; vadc: vadc@2228000 { reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; reg-names = "vadc-vafe", "vadc-vdec"; clocks = <&clks IMX6SX_CLK_VADC>, <&clks IMX6SX_CLK_CSI>; clock-names = "vadc", "csi"; + power-domains = <&pd_disp>; status = "disabled"; }; }; adc1: adc@2280000 { @@ -1361,10 +1377,11 @@ clocks = <&clks IMX6SX_CLK_PCIE_AXI>, <&clks IMX6SX_CLK_LVDS1_OUT>, <&clks IMX6SX_CLK_PCIE_REF_125M>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; - power-domains = <&pd_pci>; + power-domains = <&pd_disp>, <&pd_pci>; + power-domain-names = "pcie", "pcie_phy"; status = "disabled"; }; }; };