| Message ID | a640e9043db50f5adee8e38f5c60ff8423f3f598.1600457297.git.sathyanarayanan.kuppuswamy@linux.intel.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | Simplify PCIe native ownership detection logic | expand |
I got 1/5, 3/5, and 5/5 (and no cover letter). Is there a 2/5 and a 4/5? Not sure if I should wait for more, or review these three as-is? On Fri, Sep 18, 2020 at 12:58:30PM -0700, sathyanarayanan.kuppuswamy@linux.intel.com wrote: > From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> > > If CONFIG_PCIEPORTBUS is not enabled in kernel then initialing > struct pci_host_bridge PCIe specific native_* members to "1" is > incorrect. So protect the PCIe specific member initialization > with CONFIG_PCIEPORTBUS. > > Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> > --- > drivers/pci/probe.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index 03d37128a24f..0da0fc034413 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -588,12 +588,14 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge) > * may implement its own AER handling and use _OSC to prevent the > * OS from interfering. > */ > +#ifdef CONFIG_PCIEPORTBUS > bridge->native_aer = 1; > bridge->native_pcie_hotplug = 1; > - bridge->native_shpc_hotplug = 1; > bridge->native_pme = 1; > - bridge->native_ltr = 1; > bridge->native_dpc = 1; > +#endif > + bridge->native_ltr = 1; > + bridge->native_shpc_hotplug = 1; > > device_initialize(&bridge->dev); > } > -- > 2.17.1 >
On 9/22/20 1:39 PM, Bjorn Helgaas wrote: > I got 1/5, 3/5, and 5/5 (and no cover letter). Is there a 2/5 and a > 4/5? Not sure if I should wait for more, or review these three as-is? I sent all 5 together with cover letter. Do you want me to send it again ? > > On Fri, Sep 18, 2020 at 12:58:30PM -0700, sathyanarayanan.kuppuswamy@linux.intel.com wrote: >> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> >> >> If CONFIG_PCIEPORTBUS is not enabled in kernel then initialing >> struct pci_host_bridge PCIe specific native_* members to "1" is >> incorrect. So protect the PCIe specific member initialization >> with CONFIG_PCIEPORTBUS. >> >> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> >> --- >> drivers/pci/probe.c | 6 ++++-- >> 1 file changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c >> index 03d37128a24f..0da0fc034413 100644 >> --- a/drivers/pci/probe.c >> +++ b/drivers/pci/probe.c >> @@ -588,12 +588,14 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge) >> * may implement its own AER handling and use _OSC to prevent the >> * OS from interfering. >> */ >> +#ifdef CONFIG_PCIEPORTBUS >> bridge->native_aer = 1; >> bridge->native_pcie_hotplug = 1; >> - bridge->native_shpc_hotplug = 1; >> bridge->native_pme = 1; >> - bridge->native_ltr = 1; >> bridge->native_dpc = 1; >> +#endif >> + bridge->native_ltr = 1; >> + bridge->native_shpc_hotplug = 1; >> >> device_initialize(&bridge->dev); >> } >> -- >> 2.17.1 >>
[+cc Sean] On Tue, Sep 22, 2020 at 01:50:21PM -0700, Kuppuswamy, Sathyanarayanan wrote: > On 9/22/20 1:39 PM, Bjorn Helgaas wrote: > > I got 1/5, 3/5, and 5/5 (and no cover letter). Is there a 2/5 and a > > 4/5? Not sure if I should wait for more, or review these three as-is? > I sent all 5 together with cover letter. Do you want me to send it again ? I guess so. I'm starting to suspect something wrong with Intel's email path. Sean had a similar problem a few days ago, and he re-sent the series, and the resend also has the same problem.
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 03d37128a24f..0da0fc034413 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -588,12 +588,14 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge) * may implement its own AER handling and use _OSC to prevent the * OS from interfering. */ +#ifdef CONFIG_PCIEPORTBUS bridge->native_aer = 1; bridge->native_pcie_hotplug = 1; - bridge->native_shpc_hotplug = 1; bridge->native_pme = 1; - bridge->native_ltr = 1; bridge->native_dpc = 1; +#endif + bridge->native_ltr = 1; + bridge->native_shpc_hotplug = 1; device_initialize(&bridge->dev); }