From patchwork Wed Jun 23 13:23:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 12339843 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7748EC4743C for ; Wed, 23 Jun 2021 13:23:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6085E61075 for ; Wed, 23 Jun 2021 13:23:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231187AbhFWNZ4 (ORCPT ); Wed, 23 Jun 2021 09:25:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231193AbhFWNZz (ORCPT ); Wed, 23 Jun 2021 09:25:55 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CF4FC061756 for ; Wed, 23 Jun 2021 06:23:36 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id r7so3416008edv.12 for ; Wed, 23 Jun 2021 06:23:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sU2PjGEWCZ6p9REJDqxsU1/Bx6ufu3H69HOZKZG7O/o=; b=UCMvs7T6LglSDEVEHetpgrckvcGhBuq33yujZkz8EmBV08pEe8HxMFgrnzCmgBgaLn qc4ue3gpkOKavg5ZBg2DhvbWCSPemVD9NeyAXq8FB0CvpdRnCk645IfE9ROgK+EItULr 1MdeK/XdD0fW6ZqdnSyJ4hc1yuvos/yvDwtlzwX+SN0WuW/UurttXyvtpv8zkzK1g7Wj 21e9tjJdK2jNaUE7HeYJC8ygmmq5nUy57i3k/i1p8JhGU5gFqZdBi2tRWz34aJj7DtPy cSnp1yN+Cs5c0faZcdaxpQ7xb/0EkNtSTuk4d4iD0gXuis3HK12wTP9mvQeFEsWJ5ADt UDnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sU2PjGEWCZ6p9REJDqxsU1/Bx6ufu3H69HOZKZG7O/o=; b=dVeVs6HUz6HBgnCeS+QG65rQX+DaSuZwsHTfmxTjsY3f6PPAToAMsoQbLmqBnNddGq 0xRTOzd4KWujn87zUeSqEASse4AoGxUz0Rqab6TV1fWETqQOHkAULvfflwwPIjMMlb1V WlG1qObvYpBluTPVjOk2QoXXYIh7AZRvQ0anXlGMywEzdYQwFUrgYaPVeDn2IIOegOO5 XE23GK6fp82U1sPD9Z0zt0bsQMHzeVgIPdWAzDP/zhTnvOKzvrYKvMXSomTZ5u7SCFs4 1voYftdyGo4NH3J8yMGsADVBmbqhphf6oAF8/xtPjFeW6yIcFNt52q6tOeOya+PsyYXG E8zA== X-Gm-Message-State: AOAM531eGTnQ3Jrhca/eNdRdSDUkVS+wdQJ474KmsOvWyARaefigbXVx 8/9Uh72hsqkoIo0XC5O3kG9l1g== X-Google-Smtp-Source: ABdhPJxBXwhpnsDk4vGkm1oHbYosJ1sYshqtefU8piT3JnF1ANjAmJQrE4ECvh7GlyGRtopnMwnl8g== X-Received: by 2002:a05:6402:c03:: with SMTP id co3mr12380973edb.21.1624454615247; Wed, 23 Jun 2021 06:23:35 -0700 (PDT) Received: from localhost ([2a02:768:2307:40d6:f666:9af6:3fed:e53b]) by smtp.gmail.com with ESMTPSA id h20sm7090846ejl.7.2021.06.23.06.23.34 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 23 Jun 2021 06:23:34 -0700 (PDT) Sender: Michal Simek From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com, bharat.kumar.gogada@xilinx.com, kw@linux.com Cc: Hyun Kwon , Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Ravi Kiran Gummaluri , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org Subject: [PATCH v2 2/2] PCI: xilinx-nwl: Enable the clock through CCF Date: Wed, 23 Jun 2021 15:23:30 +0200 Message-Id: X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hyun Kwon Enable PCIE reference clock. There is no remove function that's why this should be enough for simple operation. Normally this clock is enabled by default by firmware but there are usecases where this clock should be enabled by driver itself. It is also good that clock user is recorded in clock framework. Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller") Signed-off-by: Hyun Kwon Signed-off-by: Bharat Kumar Gogada Signed-off-by: Michal Simek --- Changes in v2: - Update commit message - reported by Krzysztof - Check return value from clk_prepare_enable() - reported by Krzysztof drivers/pci/controller/pcie-xilinx-nwl.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8689311c5ef6..67639f5a5e79 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -6,6 +6,7 @@ * (C) Copyright 2014 - 2015, Xilinx, Inc. */ +#include #include #include #include @@ -169,6 +170,7 @@ struct nwl_pcie { u8 last_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; + struct clk *clk; raw_spinlock_t leg_mask_lock; }; @@ -823,6 +825,16 @@ static int nwl_pcie_probe(struct platform_device *pdev) return err; } + pcie->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pcie->clk)) + return PTR_ERR(pcie->clk); + + err = clk_prepare_enable(pcie->clk); + if (err) { + dev_err(dev, "can't enable pcie ref clock\n"); + return err; + } + err = nwl_pcie_bridge_init(pcie); if (err) { dev_err(dev, "HW Initialization failed\n");