From patchwork Mon Nov 23 09:28:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 7678361 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5A878BF90C for ; Mon, 23 Nov 2015 09:30:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8BE9E2061D for ; Mon, 23 Nov 2015 09:30:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A3F2F205EF for ; Mon, 23 Nov 2015 09:30:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753511AbbKWJ3t (ORCPT ); Mon, 23 Nov 2015 04:29:49 -0500 Received: from mail-wm0-f50.google.com ([74.125.82.50]:35668 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754160AbbKWJ3h (ORCPT ); Mon, 23 Nov 2015 04:29:37 -0500 Received: by wmuu63 with SMTP id u63so45491020wmu.0 for ; Mon, 23 Nov 2015 01:29:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=GmRPHWdfMz2wD3vWk02WozJWW5F52Etr8mPuH57gHIc=; b=f+2vS4r6J46lk/f5OSG6M7ljz3+BntqIcvxahWrCG2YWaNzpT31phcJWm0Cf1Zs51w MrPFflqppopsYgfRzMEH4Li9CDS7LfQu9UbyPZ1ap+DDmHba3P0bAnTvHIHnmK+D9JTG tFMHJ0j/DBCYOY8OOYmYoevro9Y8u8/RnInZ138qoct8X/AhtknXqxoSM76C3lHFGdLN aMYB3APaS5BYFlOTFheb3RZtPZPFuyV8yDETaFuRrtkovmZ6L9qScAVus2Do+fyYCCgn O5DhKCZ+1UgZjAnADuUs/Cw67R8ymFlxH4/L9rK4Sq1Q2kVaO29f8DePlnrz6wIJmVBK DKig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=GmRPHWdfMz2wD3vWk02WozJWW5F52Etr8mPuH57gHIc=; b=IEaThk3ZGOFHu6NEwlRopjcK3vkN4oyj8Tu9MJ3UEFKQXnsm/ALfRnl23aUiaEFFm2 8ecvTO+UDGSEabngB+rcAWqsh5HpWtDxZkzCMzzqHbsMAkVvakl06WCidrjYfaY80BsX npcFVUvIlblvCohDDUvlJvaDJWz161oHjgynHTO/VXdRqbUhnvKjCh4ZN4wr2JWe4Ror Y8Svd+XliOFmaFUaA618EGRlu63PPQWR4+dwQ0ierdZ+gbe6ElK8pUmPHPiH9a7UE3Sh BhPgRDdYDBS6nAfmT/PR4ps2z+64fJ1l8zDbR4ZI8VfCjmuvCVjthqFG/ZuygsR5ilLi 7idw== X-Gm-Message-State: ALoCoQmlMahbRn/8l+NB2UqLv3l6231RvnHRwLcvOOPuY0XzGTEekDPyu2zCek+0FBszuTsi8ILk X-Received: by 10.194.23.33 with SMTP id j1mr29127198wjf.4.1448270976401; Mon, 23 Nov 2015 01:29:36 -0800 (PST) Received: from mms734.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.gmail.com with ESMTPSA id k125sm5547508wmf.2.2015.11.23.01.29.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Nov 2015 01:29:35 -0800 (PST) From: Stanimir Varbanov To: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Bjorn Helgaas Cc: Srinivas Kandagatla , Rob Herring , Rob Herring , Mark Rutland , Pawel Moll , Ian Campbell , Arnd Bergmann , Jingoo Han , Pratyush Anand , Bjorn Andersson , Stanimir Varbanov Subject: [PATCH v3 2/6] PCI: designware: add memory barrier after enabling region Date: Mon, 23 Nov 2015 11:28:59 +0200 Message-Id: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add 'write memory' barrier after enable region in PCIE_ATU_CR2 register. The barrier is needed to ensure that the region enable request has been reached it's destination at time when we read/write to PCI configuration space. Without this barrier PCI device enumeration during kernel boot is not reliable, and reading configuration space for particular PCI device on the bus returns zero aka no device. Signed-off-by: Stanimir Varbanov --- drivers/pci/host/pcie-designware.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 02a7452bdf23..e15a2ae1583f 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -164,6 +164,11 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET); dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); + /* + * ensure that the ATU enable has been happaned before accessing + * pci configuration/io spaces through dw_pcie_cfg_[read|write]. + */ + smp_wmb(); } static struct irq_chip dw_msi_irq_chip = {