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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?hXx1rx6NY1ySNwqiYI+xpd9n+e3g?= =?utf-8?q?OzL1Oa8lu+X+62iD9OULnPbYH+BdR5ZiCjeM0yO3q1Ad414Xbozc5MqL8butG5Zy+?= =?utf-8?q?ZVsj7iP7XKmPLet3dBlDkUWpBUKmQK9LtY+GpX/ssM9jubFFag7jNJSqTyZKZvXJw?= =?utf-8?q?b0ghcutbiQOi4Kv0nJX6IPT5gzVUxWoUo5LVB/zFg/PH3e8e+TZ0dEGO1rfxrjmxo?= =?utf-8?q?DFDK/Fg4dkgyiT4R9UDBlXd8SIJikUsJL7S4QvAtalZg5V3R1S3IpL8ypgdc5+gXx?= =?utf-8?q?XTPV7xtvE1GI+c1IEgy326kiR4gYJYGFtfYTY65lM4OUdJz/pcf/cdihd0BUTJO3M?= =?utf-8?q?6sXyhCuDnWR5FVac2pKxHnUpaqRifV+TLVuKE6RGkAu9ceh+YngogkXov9ZeykdTl?= =?utf-8?q?R0kyIGsmoK9V6VDu7p+hZF1hD6RVK5oEEe1NAWyw5BXGxlPpMpbX0pgVwTLkbzi4+?= =?utf-8?q?moe2l0SR7vKBRPrIuhvRtZTjUiezb3k0R++F4GYB0Q/rNcem/Van0TrRxxXx6+eXU?= =?utf-8?q?c8xumcG4lh39jOgF8tDltBVWs69UyChdVqf+x//GKIyV6q+VzYqgpkrpTa2nm1kfv?= =?utf-8?q?dm2X3adbpkF15hzt7EA8IHWtx2oLNtIByV6tUfDhCnkffQBInNtUOov+tJgaaLBSR?= =?utf-8?q?KRVO0HiRpghm2Lq+BG9WUWnLnhFtdDI9FvJTfJpsJ4MKY7rBt95b/PI9dznJqrBb4?= =?utf-8?q?UdBivuVydelEWrXMETgKnxJjmZuQrxrpq/KnD9vr2O8G2jIoQzSGkzrXugplyufVW?= =?utf-8?q?WCFhRIjkSjVIDzl1R8DM/kl/qEH2k+EjqTIIXfROODyikiCtfZoe3wLsjUg6z60QJ?= =?utf-8?q?8JGX0GzIVj/2xMc1wcU81Dp7HFN07CLAlxavf1p3zVmnTiIzpN2p9jNHYaQCAnQqn?= =?utf-8?q?fvVmxrnMM8krdp6S0C7XiIheoOC828pahBaAJoYRH/n3EOc0fHOk9JpN7SFeiQ3sb?= =?utf-8?q?F7HLc8RJ6ECiHYBkCsm14b3sp5kXoPhP7RIZA8iTWW7kjXGGkI3ZNOv3rH/xSMsqh?= =?utf-8?q?qR6TE8okYOiK55ceSWsPfEO+LlN+PZ83J4XKEJmbHlDkNFe1fi+47HLMmMyC1FfT0?= =?utf-8?q?IOyNV7nxh8VIcwOtNoHF6YU6n2WAcjdqYYwTCc6jnp5bVUZaGDahxgMIipNu7SP8N?= =?utf-8?q?x9al+3EmYiZNQr1pMmHiU3BOFY558vx3asY1weR6QrC+xM67TYDg7d0L7iderB3Vt?= =?utf-8?q?C6HCDNvR95A/+/1PDVWrfGEUwZFnvjID9R48HmTKEw0I7lvCXEv8KhU5pCDOLL4jv?= =?utf-8?q?PaeuXwkUvjaSM1B0SqnCAaYfNzuc1k9uqA+KxbixWTNB3KhIpBJ9736UsFPC5Ez0M?= =?utf-8?q?rTE8LPXXyH6zKTRe2GGMgCCA8laXS3TIS+g1bmpITFwHueg9Q2j8RYkG8zhOf5INa?= =?utf-8?q?puaFOvgnPvJOJkF+C/u5atpQmtWcg+6ofH7FmCAmrbTiOGs3de61ns5O12+9kpUbm?= =?utf-8?q?z/d4ikdYPLEyP3ydv4Wf0xsev90+w2xdqO8aigIImYn6mzFZQZbz/uVbUdqsSUBin?= =?utf-8?q?I4n0OgPzCNO+?= X-OriginatorOrg: siemens.com X-MS-Exchange-CrossTenant-Network-Message-Id: 98b0cc00-4dc1-4e0f-946a-08dc97399a68 X-MS-Exchange-CrossTenant-AuthSource: AS4PR10MB6181.EURPRD10.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2024 06:14:43.9984 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 38ae3bcd-9579-4fd4-adda-b42e1495d55a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /hIi/G+iYj/3ovbv320jT+v0yxUbhFmobRjHFLZV40FyiSBtJwqrnlrdy5kDoGT5IGmNt7Tx25yggfDN97x3pA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR10MB7499 From: Kishon Vijay Abraham I Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an inbound PCIe TLP spans more than two internal AXI 128-byte bursts, the bus may corrupt the packet payload and the corrupt data may cause associated applications or the processor to hang. The workaround for Errata #i2037 is to limit the maximum read request size and maximum payload size to 128 bytes. Add workaround for Errata #i2037 here. The errata and workaround is applicable only to AM65x SR 1.0 and later versions of the silicon will have this fixed. [1] -> http://www.ti.com/lit/er/sprz452d/sprz452d.pdf Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Achal Verma Signed-off-by: Vignesh Raghavendra Signed-off-by: Jan Kiszka Reviewed-by: Siddharth Vadapalli --- Original patch: Link: https://lore.kernel.org/linux-pci/20210325090026.8843-7-kishon@ti.com/ --- drivers/pci/controller/dwc/pci-keystone.c | 44 ++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d3a7d14ee685..25e365c0c5c7 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -34,6 +34,11 @@ #define PCIE_DEVICEID_SHIFT 16 /* Application registers */ +#define PID 0x000 +#define RTL GENMASK(15, 11) +#define RTL_SHIFT 11 +#define AM6_PCI_PG1_RTL_VER 0x15 + #define CMD_STATUS 0x004 #define LTSSM_EN_VAL BIT(0) #define OB_XLAT_EN_VAL BIT(1) @@ -104,6 +109,8 @@ #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +#define PCI_DEVICE_ID_TI_AM654X 0xb00c + struct ks_pcie_of_data { enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; @@ -525,7 +532,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci) static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; + struct keystone_pcie *ks_pcie; + struct device *bridge_dev; struct pci_dev *bridge; + u32 val; + static const struct pci_device_id rc_pci_devids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, @@ -537,6 +548,11 @@ static void ks_pcie_quirk(struct pci_dev *dev) .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, { 0, }, }; + static const struct pci_device_id am6_pci_devids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { 0, }, + }; if (pci_is_root_bus(bus)) bridge = dev; @@ -558,10 +574,36 @@ static void ks_pcie_quirk(struct pci_dev *dev) */ if (pci_match_id(rc_pci_devids, bridge)) { if (pcie_get_readrq(dev) > 256) { - dev_info(&dev->dev, "limiting MRRS to 256\n"); + dev_info(&dev->dev, "limiting MRRS to 256 bytes\n"); pcie_set_readrq(dev, 256); } } + + /* + * Memory transactions fail with PCI controller in AM654 PG1.0 + * when MRRS is set to more than 128 bytes. Force the MRRS to + * 128 bytes in all downstream devices. + */ + if (pci_match_id(am6_pci_devids, bridge)) { + bridge_dev = pci_get_host_bridge_device(dev); + if (!bridge_dev && !bridge_dev->parent) + return; + + ks_pcie = dev_get_drvdata(bridge_dev->parent); + if (!ks_pcie) + return; + + val = ks_pcie_app_readl(ks_pcie, PID); + val &= RTL; + val >>= RTL_SHIFT; + if (val != AM6_PCI_PG1_RTL_VER) + return; + + if (pcie_get_readrq(dev) > 128) { + dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); + pcie_set_readrq(dev, 128); + } + } } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);