From patchwork Tue Aug 9 16:35:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joao Pinto X-Patchwork-Id: 9271739 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1C30A60754 for ; Tue, 9 Aug 2016 16:36:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0D58727569 for ; Tue, 9 Aug 2016 16:36:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0234128375; Tue, 9 Aug 2016 16:36:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9CEC727569 for ; Tue, 9 Aug 2016 16:36:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932579AbcHIQgT (ORCPT ); Tue, 9 Aug 2016 12:36:19 -0400 Received: from smtprelay2.synopsys.com ([198.182.60.111]:43899 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932442AbcHIQfm (ORCPT ); Tue, 9 Aug 2016 12:35:42 -0400 Received: from us02secmta2.synopsys.com (us02secmta2.synopsys.com [10.12.235.98]) by smtprelay.synopsys.com (Postfix) with ESMTP id 6E25610C1461; Tue, 9 Aug 2016 09:35:41 -0700 (PDT) Received: from us02secmta2.internal.synopsys.com (us02secmta2.internal.synopsys.com [127.0.0.1]) by us02secmta2.internal.synopsys.com (Service) with ESMTP id 606DE55F13; Tue, 9 Aug 2016 09:35:41 -0700 (PDT) Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by us02secmta2.internal.synopsys.com (Service) with ESMTP id 31ED055F02; Tue, 9 Aug 2016 09:35:41 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 1D10EBD0; Tue, 9 Aug 2016 09:35:41 -0700 (PDT) Received: from jppCent.internal.synopsys.com (jppcent.internal.synopsys.com [10.107.19.121]) by mailhost.synopsys.com (Postfix) with ESMTP id 9A275BC1; Tue, 9 Aug 2016 09:35:39 -0700 (PDT) From: Joao Pinto To: helgaas@kernel.org Cc: jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, jszhang@marvell.com, Joao Pinto Subject: [PATCH v4 1/3] pcie-designware: move definitions Date: Tue, 9 Aug 2016 17:35:32 +0100 Message-Id: X-Mailer: git-send-email 1.8.1.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch moves the sleep definitions to the *.c file like suggested by Jisheng Zhang in a previous patch. Signed-off-by: Joao Pinto CC: Jisheng Zhang --- changes v3->v4: - Just to keep up with the patch version changes v2->v3 (Bjorn Helgaas): - Separated from the new iATU unroll mechanism patch drivers/pci/host/pcie-designware.c | 5 +++++ drivers/pci/host/pcie-designware.h | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 12afce1..6fb88de 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -26,6 +26,11 @@ #include "pcie-designware.h" +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + /* Synopsis specific PCIE configuration registers */ #define PCIE_PORT_LINK_CONTROL 0x710 #define PORT_LINK_MODE_MASK (0x3f << 16) diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index f437f9b..384e79b 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -22,11 +22,6 @@ #define MAX_MSI_IRQS 32 #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - struct pcie_port { struct device *dev; u8 root_bus_nr;