From patchwork Fri Mar 25 13:32:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Krzysztof_Ha=C5=82asa?= X-Patchwork-Id: 8671511 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 559EBC0553 for ; Fri, 25 Mar 2016 13:32:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 58ADC20357 for ; Fri, 25 Mar 2016 13:32:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 13DA4202AE for ; Fri, 25 Mar 2016 13:32:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752171AbcCYNck (ORCPT ); Fri, 25 Mar 2016 09:32:40 -0400 Received: from ni.piap.pl ([195.187.100.4]:60785 "EHLO ni.piap.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751940AbcCYNcj convert rfc822-to-8bit (ORCPT ); Fri, 25 Mar 2016 09:32:39 -0400 Received: from t19.piap.pl (OSB1819.piap.pl [10.0.9.19]) by ni.piap.pl (Postfix) with ESMTP id A8AD44413ED; Fri, 25 Mar 2016 14:32:35 +0100 (CET) From: khalasa@piap.pl (Krzysztof =?utf-8?Q?Ha=C5=82asa?=) To: Petr =?utf-8?Q?=C5=A0tetiar?= , Richard Zhu , Lucas Stach , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] i.MX6 PCIe: Fix imx6_pcie_deassert_core_reset() polarity Date: Fri, 25 Mar 2016 14:32:35 +0100 Message-ID: MIME-Version: 1.0 X-KLMS-Rule-ID: 1 X-KLMS-Message-Action: clean X-KLMS-AntiSpam-Lua-Profiles: 93578 [Mar 25 2016] X-KLMS-AntiSpam-Version: 5.5.9.33 X-KLMS-AntiSpam-Envelope-From: khalasa@piap.pl X-KLMS-AntiSpam-Rate: 0 X-KLMS-AntiSpam-Status: not_detected X-KLMS-AntiSpam-Method: none X-KLMS-AntiSpam-Moebius-Timestamps: 4033847, 4033871, 4033855 X-KLMS-AntiSpam-Info: LuaCore: 415 415 56d27afa4611b5fc17406ce7708f83a66d615280, Auth:dkim=none X-KLMS-AntiSpam-Interceptor-Info: scan successful X-KLMS-AntiPhishing: Clean, 2016/03/24 15:12:18 X-KLMS-AntiVirus: Kaspersky Security 8.0 for Linux Mail Server, version 8.0.1.721, bases: 2016/03/25 05:36:00 #7328597 X-KLMS-AntiVirus-Status: Clean, skipped Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A recent commit 5c5fb40de8f14391a1238db05cef88754faf9229 stated: Follows: linus/v4.4-rc2 Precedes: linus/v4.5-rc1 PCI: imx6: Add support for active-low reset GPIO We previously used of_get_named_gpio(), which ignores the OF flags cell, so the reset GPIO defaulted to "active high." This doesn't work on the Toradex Apalis SoM with Ixora base board, which has an active-low reset GPIO. Use devm_gpiod_get_optional() instead so we pay attention to the active high/low flag. This also adds support for GPIOs described via ACPI. The (now replaced) code doesn't support the above: @@ -287,10 +287,10 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) usleep_range(200, 500); /* Some boards don't have PCIe reset GPIO. */ - if (gpio_is_valid(imx6_pcie->reset_gpio)) { - gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0); + if (imx6_pcie->reset_gpio) { + gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 0); msleep(100); - gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1); + gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1); } return 0; If the reset_gpio setup code had ignored the flags (haven't checked that), then clearly the resets were active-low (most reset lines are, because they can be then driven with open-drain/collector output). The gpiod_set_value*(0) activates reset, gpiod_set_value(1) - deactivates. Now we're told the setup code is now level-aware, but the above sequence thus _deactivates_ reset for 100 ms, then _activates_ it again. It has no chance to work, unless a board has a broken DTS file. A quick grep shows that about half the IMX6 boards specify an active-low PCIe reset, 4 ask for active-high, and another 4 don't bother. I wonder if all boards (except maybe that Toradex set) use an active-low PCIe reset and are now broken. Perhaps Toradex uses active-high and thus works. I'm not fixing individual DTS files because I don't really know, though perhaps we should change them all to "active-low", since it would work the same as before the 5c5fb40de8f14391a1238db05cef88754faf9229 change. Confirmed to fix Gateworks Laguna GW54xx. Without the patch, the following happens (as expected): PCI host bridge /soc/pcie@0x01000000 ranges: No bus range found for /soc/pcie@0x01000000, using [bus 00-ff] IO 0x01f80000..0x01f8ffff -> 0x00000000 MEM 0x01000000..0x01efffff -> 0x01000000 imx6q-pcie 1ffc000.pcie: phy link never came up Signed-off-by: Krzysztof Ha?asa Reviewed-by: Fabio Estevam --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index fe60096..f17fb02 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -288,9 +288,9 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) /* Some boards don't have PCIe reset GPIO. */ if (imx6_pcie->reset_gpio) { - gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 0); - msleep(100); gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1); + msleep(100); + gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 0); } return 0;