| Message ID | 20210310120840.16447-1-kishon@ti.com |
|---|---|
| Headers | show |
| Series | AM64: Add SERDES driver support | expand |
Hi, On 10/03/21 5:38 pm, Kishon Vijay Abraham I wrote: > AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't > have a clock generator (unlike J7200 base board). Here the clock from > the SERDES has to be routed to the PCIE connector. This series adds > support to drive reference clock output from SERDES and also adds > SERDES (torrent) and SERDES wrapper (WIZ) bindings. > > v1 of the patch series can be found @ [1] > v2 of the patch series can be found @ [3] Failed to note the dependency here. This series depends on http://lore.kernel.org/r/20210310112745.3445-1-kishon@ti.com As mentioned in the cover letter of that patch series, that series should be merged and an immutable tag should be provided and used both in phy tree and DT tree maintained by Nishanth. Thanks Kishon > > Changes from v2: > *) Sent the DT bindings as a separate series [4] > *) Remove enabling PHY output clock in isolation mode > > Changes from v1: > *) Model the internal clocks without device tree input (Add #clock-cells > to SERDES DT nodes for getting a reference to the clock using index > to phandle). This is in accordance with comment given by Rob [2]. > However the existing method to model clocks from device tree is not > removed to support upstreamed device tree. > *) Included a patch to fix modifying static data by instance specific > initializations. > *) Added a fix to delete "clk_div_sel" clk provider during cleanup > > [1] -> https://lore.kernel.org/r/20201224114250.1083-1-kishon@ti.com > [2] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.org > [3] -> http://lore.kernel.org/r/20210222112314.10772-1-kishon@ti.com > [4] -> http://lore.kernel.org/r/20210310112745.3445-1-kishon@ti.com > > Kishon Vijay Abraham I (6): > phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_sel > phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup > phy: ti: j721e-wiz: Configure full rate divider for AM64 > phy: ti: j721e-wiz: Model the internal clocks without device tree > input > phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m> > phy: cadence-torrent: Add support to drive refclk out > > drivers/phy/cadence/Kconfig | 1 + > drivers/phy/cadence/phy-cadence-torrent.c | 188 +++++++++++- > drivers/phy/ti/phy-j721e-wiz.c | 349 +++++++++++++++++++--- > 3 files changed, 488 insertions(+), 50 deletions(-) >
On 10-03-21, 17:38, Kishon Vijay Abraham I wrote: > AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't > have a clock generator (unlike J7200 base board). Here the clock from > the SERDES has to be routed to the PCIE connector. This series adds > support to drive reference clock output from SERDES and also adds > SERDES (torrent) and SERDES wrapper (WIZ) bindings. > > v1 of the patch series can be found @ [1] > v2 of the patch series can be found @ [3] > > Changes from v2: > *) Sent the DT bindings as a separate series [4] > *) Remove enabling PHY output clock in isolation mode > > Changes from v1: > *) Model the internal clocks without device tree input (Add #clock-cells > to SERDES DT nodes for getting a reference to the clock using index > to phandle). This is in accordance with comment given by Rob [2]. > However the existing method to model clocks from device tree is not > removed to support upstreamed device tree. > *) Included a patch to fix modifying static data by instance specific > initializations. > *) Added a fix to delete "clk_div_sel" clk provider during cleanup Applied, thanks
AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't have a clock generator (unlike J7200 base board). Here the clock from the SERDES has to be routed to the PCIE connector. This series adds support to drive reference clock output from SERDES and also adds SERDES (torrent) and SERDES wrapper (WIZ) bindings. v1 of the patch series can be found @ [1] v2 of the patch series can be found @ [3] Changes from v2: *) Sent the DT bindings as a separate series [4] *) Remove enabling PHY output clock in isolation mode Changes from v1: *) Model the internal clocks without device tree input (Add #clock-cells to SERDES DT nodes for getting a reference to the clock using index to phandle). This is in accordance with comment given by Rob [2]. However the existing method to model clocks from device tree is not removed to support upstreamed device tree. *) Included a patch to fix modifying static data by instance specific initializations. *) Added a fix to delete "clk_div_sel" clk provider during cleanup [1] -> https://lore.kernel.org/r/20201224114250.1083-1-kishon@ti.com [2] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.org [3] -> http://lore.kernel.org/r/20210222112314.10772-1-kishon@ti.com [4] -> http://lore.kernel.org/r/20210310112745.3445-1-kishon@ti.com Kishon Vijay Abraham I (6): phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_sel phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup phy: ti: j721e-wiz: Configure full rate divider for AM64 phy: ti: j721e-wiz: Model the internal clocks without device tree input phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m> phy: cadence-torrent: Add support to drive refclk out drivers/phy/cadence/Kconfig | 1 + drivers/phy/cadence/phy-cadence-torrent.c | 188 +++++++++++- drivers/phy/ti/phy-j721e-wiz.c | 349 +++++++++++++++++++--- 3 files changed, 488 insertions(+), 50 deletions(-)