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[83.51.243.231]) by smtp.gmail.com with ESMTPSA id b12sm11638010wro.28.2021.05.07.23.52.34 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 May 2021 23:52:34 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: linux-phy@lists.infradead.org, kishon@ti.com, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH v2 0/6] phy: ralink: mt7621-pci-phy: some improvements Date: Sat, 8 May 2021 08:52:26 +0200 Message-Id: <20210508065232.4882-1-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210507_235236_788220_F061D152 X-CRM114-Status: GOOD ( 16.46 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi all, This series contains some improvements in the pci phy driver for MT7621 SoCs. MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' Because of this we can update schema documentation and device tree to add related clock entries and avoid custom architecture code in favour of using the clock kernel framework to retrieve clock frequency needed to properly configure the PCIe related Phys. After this changes there is no problem to properly enable this driver for COMPILE_TEST. Configuration has also modified from 'tristate' to 'bool' depending on PCI_MT7621 which seems to have more sense. Thanks in advance for your time. Changes in v2: - Drop 'clock-names' property from device tree and binding doc sice only one clock is needed. - Update driver code to don't get clock name as identifier for the clock but just use NULL. - Add patch to fix a COMPILE_TEST reported issue because of the way printing of a pointer was being done. This patch was already send by its own[0] but to have all of this applied together I prefer to include it here. Best regards, Sergio Paracuellos [0]: http://lists.infradead.org/pipermail/linux-phy/2021-May/000395.html Sergio Paracuellos (6): staging: mt7621-dts: use clock in pci phy nodes dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries phy: ralink: phy-mt7621-pci: use kernel clock APIS phy: ralink: Kconfig: enable COMPILE_TEST on mt7621-pci-phy driver phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool' phy: ralink: phy-mt7621-pci: properly print pointer address .../bindings/phy/mediatek,mt7621-pci-phy.yaml | 5 +++ drivers/phy/ralink/Kconfig | 4 +- drivers/phy/ralink/phy-mt7621-pci.c | 37 +++++++++++-------- drivers/staging/mt7621-dts/mt7621.dtsi | 2 + 4 files changed, 31 insertions(+), 17 deletions(-)